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boards/nucleo-{f207zg,f746zg,f767zi}: periph_eth

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Use shared MII register definitions from mii.h rather than own definitions.
This commit is contained in:
Marian Buschsieweke 2020-10-09 20:12:16 +02:00
parent 6294382627
commit bedddce263
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GPG Key ID: 61F64C6599B1539F
3 changed files with 6 additions and 3 deletions
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3
boards/nucleo-f207zg/include/periph_conf.h
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@ -35,6 +35,7 @@
#include "f2f4f7/cfg_clock_default_120.h"
#include "cfg_i2c1_pb8_pb9.h"
#include "cfg_usb_otg_fs.h"
#include "mii.h"
#ifdef __cplusplus
extern "C" {
@ -248,7 +249,7 @@ static const adc_conf_t adc_config[] = {
static const eth_conf_t eth_config = {
.mode = RMII,
.addr = { 0 },
.speed = ETH_SPEED_100TX_FD,
.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX,
.dma = 6,
.dma_chan = 8,
.phy_addr = 0x00,

3
boards/nucleo-f746zg/include/periph_conf.h
View File

@ -35,6 +35,7 @@
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
#include "cfg_usb_otg_fs.h"
#include "mii.h"
#ifdef __cplusplus
extern "C" {
@ -219,7 +220,7 @@ static const spi_conf_t spi_config[] = {
static const eth_conf_t eth_config = {
.mode = RMII,
.addr = { 0 },
.speed = ETH_SPEED_100TX_FD,
.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX,
.dma = 7,
.dma_chan = 8,
.phy_addr = 0x00,

3
boards/nucleo-f767zi/include/periph_conf.h
View File

@ -35,6 +35,7 @@
#include "cfg_rtt_default.h"
#include "cfg_timer_tim2.h"
#include "cfg_usb_otg_fs.h"
#include "mii.h"
#ifdef __cplusplus
extern "C" {
@ -167,7 +168,7 @@ static const spi_conf_t spi_config[] = {
static const eth_conf_t eth_config = {
.mode = RMII,
.addr = { 0 },
.speed = ETH_SPEED_100TX_FD,
.speed = MII_BMCR_SPEED_100 | MII_BMCR_FULL_DPLX,
.dma = 3,
.dma_chan = 8,
.phy_addr = 0x00,