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Commit Graph

9 Commits

Author SHA1 Message Date
Ollrogge
b21640f1e0 cpu/riscv_common: fix undeclared memory region linker error 2022-04-04 13:18:01 +02:00
chrysn
facb5e633f
Merge pull request #17436 from Ollrogge/reserve_flash
cpu: add flash_writable section to linker script
2022-03-17 21:44:32 +01:00
Ollrogge
74d086cdd6 cpu/riscv_common: add flash_writable section to linker script 2022-03-07 11:25:38 +01:00
PeterKietzmann
992e09b07b cpu/riscv_common: add bss end to clear memory 2022-02-16 10:52:09 +01:00
PeterKietzmann
dd4fe70a62 cpu/riscv_common: add noinit section to ld script 2022-02-16 10:48:31 +01:00
Sören Tempel
e41063d40e cpu/riscv_common: fix undeclared memory region linker error
Since commit 3a11b1fbd2 (#16972)
building RIOT applications with `BOARD=hifive1` causes the following
linker error to be emitted on my system:

	/opt/rv32imc/lib/gcc/riscv32-unknown-elf/10.2.0/../../../../riscv32-unknown-elf/bin/ld:riscv_base.ld:220: warning: memory region `rom' not declared

This is due to the fact that the RISC-V linker script doesn't have a rom
memory region. While many other ARM-based boards have a rom memory
region defined in the linker script, the corresponding region name in
the RISC-V linker script is flash and rom is not declared as a memory
region hence the warning.

I think this was accidentally overlooked in
3a11b1fbd2. It is fixed in this commit by
replacing the rom region with the flash region. The linker script
identifiers (e.g. _srom and _erom) are not renamed.
2022-01-27 15:02:50 +01:00
Ollrogge
3a11b1fbd2 cpu/riscv_common: extend flashpage API 2021-10-25 15:07:37 +02:00
b3b04faadb cpu/fe310: add XFA support 2021-02-18 10:46:08 +01:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00