Currently the configuration claims that external interrupt INT4 is present on
pin PE7. However, the ATmega32U4 datasheet (section 10.3.4 page 81) contains
the following remark to pin PE7: "Not present on pin-out". This commit removes
the PE7 from the interrupt config.
- Moved VIC.c to irq_arch.c for consistent naming scheme
- Removed unused functions IRQenabled, disableFIQ, restoreFIQ, enableFIQ
- There is not header for those functions, so they *cannot* be used
- These is obviously no user, as they *cannot* be used
- There is absolutely no documentation what they would be used for
The `mips32r2_generic` CPU was only used by the `mips-malta` board which has
been removed. The reasons for this removal are the same as for the board:
- No hardware to test.
- The board that used this CPU is not available off the shelf.
- No UART input.
- No integrated flasher (one needs to use a separate Windows tool)
For more information and discussion around MIPS, see issues:
- #11831 (Removal of mips-malta)
- #11788 (General MIPS removal)
cpu/stm32_common: cleanup periph eth
boards/nucleo-f767zi: cleanup dependencies
boards/nucleo-f767zi: fix dma configuration attribute for eth
examples/default: add nucleo-767zi in boards with netif
drivers/stm_32_eth: Add header guard for eth_config
Co-authored-By: Robin <robin@chilio.net>
stm32eth: Move to stm32_common periph
cpu/stm32_periph_eth: Rebase to current master branch
- Update DMA to use new vendor headers
- Update send to use iolist. It looks like the packet headers are now transfered as seperate iolist entries which results in the eth periph sending each header as own packet. To fix this a rather ugly workaround is used where the whole iolist content is first copied to a static buffer. This will be fixed soon in another commit
- If MAC is set to zero use luid to generate one
- Small code style fixes
cpu/stm312f7: Add periph config for on-board ethernet
boards/nucleo-f767zi: Add config for on board ethernet
tests/stm32_eth_lwip: Remove board restriction
boards/common/nucleo: Add luid module if stm32 ethernet is used
tests/stm32_eth_gnrc: Add Testcase for gnrc using the stm32 eth periph
stm32_eth: Rework netdev driver layour
tests/stm32_eth_*: Use netdev driver header file for prototypes
stm32_eth: Add auto init for stm32 eth netdev driver
boards/stm32: Enable ethernet conf for nucleo boards
stm32_eth_auto_init: Add dont be pendantic flag
stm32_eth: Remove dma specific stuff from periph_cpu.h
Looks like this was implemented in PR #9171 and 021697ae94 with the same interface.
stm32_eth: Remove eth feature from stm32f4discovery boards
stm32_eth: Migrate to stm32 DMA API
stm32_eth: Add iolist to module deps
stm32_eth: Rework send function to use iolist
stm32_eth: Fix ci build warnings
stm32_eth: Fix bug introduced with iolist usage
stm32_eth: Remove redundant static buffer
stm32_eth: Fix feature dependencies
stm32_eth: Fix wrong header guard name
stm32_eth: Implement correct l2 netstats interface
stm32_eth: Rename public functions to stm32_eth_*
stm32_eth: Fix doccheck
stm32_eth: Move register DEFINE to appropriate header file
stm32_eth: remove untested configuration for f446ze boards
stm32_eth: Move periph configuration struct to stm32_common
stm32_eth: Fix naming of eth_phy_read and eth_phy_write
stm32_eth: Remove obsolete test applications
drivers/eth-phy: add generic Ethernet PHY iface
cpu/stm32f4: implement eth driver peripheral
This implements the ethernet (MAC) peripheral of the stm32f4 as a
netdev driver.
boards/stm32f4discovery: add eth configuration
boards/stm32f4discovery: add feature stm32_eth
tests/stm32_eth_lwip: add test application
- EOP bit is cleared by writing 1 to the register.
- Guard EOP bit clear for STM32F2, STM32F4, STM32F7
and STM32L4 EOP bit is only set if EOPIE is enabled.
Since this is not the case for any platform we exclude
it when not needed.
- With this PR, On start up all GPIOs are configured as AIN. For stm32l0/4
this is done by default. Doing this saves the consumption of the input Schmitt
trigger in STOP mode which can reduce the consumption in at least 70%
from current master.
- The PNB in FLASH_CR wasn't cleared before every erase operation
and the new value was just stacked on top. After a couple of erase
the PNB written was overlapping with old ones failing to erase the
correct page.
In the `pwm_set` function, the switch-on and switch-off times for PWM channels were only determined for the following phase, but not for the current phase. This could result in a missing duty cycle when calling the function `pwm_set` if the switch-on time of the current phase was not yet reached or to an extended duty cycle if the switch-off time of the current phase had not yet been reached.
On cppcheck 1.82 it throws a warning.
Since it costs cycles and does nothing the ++dummy is (void)dummy.
A warning suppression is added so the CI is happy.
This fixes the positive result when master write data is NACKed.
This false positive occurs when the write frame is finished but a data nack occurred.
The AF check should occur first.
This commit fixes the clearing of a error condition after read.
This causes the incorrect errorcodes if the register is read
then an error occurs, then it is cleared.
By clearing only after the error is processed the bug is fixed.
This can be tested by reading a i2c slave that is not there.
There were still some things wrong with samd5x CPU init which only
showed up when used in conjunction with RIOTBOOT, that is cpu_init()
was called twice.
- gclk_connect() should block until the GCLK is ready.
- DPLL should be disabled dring configuration.
- make sure not to use DPLL for MCLK when re-configuring DPLL
- All APBxMASK bits should be in a defined state.
- always enable 1kHz oscilator output.
- Before, HSI was enabled as the default case when it is only
used for stm32f0 and stm32f1. It is now implemented explicitly
for those platforms, and only those.
- Since the Vector table must be naturally aligned to the next power
of two of the amount of supported ISR, and the table will be
placed after riotboot_hdr, we must ensure RIOTBOOT_HRD_LEN has the
same alignment.
This adds supoprt for the Atmel SAMD51 & SAME54 SoC.
The SAME5x/SAMD5x is a line of Cortex-M4F MCUs that share peripherals
with the samd2x Cortex-M0+ and saml1x Cortex-M23 parts.
Atmel Software Framework (ASF) provides a set of low-level header files
that give access to different hardware peripherals of Atmel's ICs.
Origin: Atmel SAMD51 Series Device Support (1.1.96)
License: Apache-2.0
URL: http://packs.download.atmel.com/Atmel.SAMD51_DFP.1.1.96.atpack
Atmel Software Framework (ASF) provides a set of low-level header
files that give access to different hardware peripherals of Atmel's
ICs.
Origin: Atmel SAME54 Series Device Support (1.0.87)
License: Apache-2.0
URL: http://packs.download.atmel.com/Atmel.SAME54_DFP.1.0.87.atpack
This cleans up the sam0 timer driver:
- remove the check for the unused freq parameter
- the MCU provides dedicated SET/CLR registers to avoid
read-modify-write, so don't do read-modify-write on them.
- workaround a possible hardware bug on SAMD5x:
loop until the CMD_READSYNC is really set
This change required correcting the values for LCRH_PEN and LRCH_EPS
values defined in cc26x0_uart.h, as they were incorrect according to
19.8.1.7 of the TI CC26x0 reference manual.
on-behalf-of: @sparkmeter <ben.postman@sparkmeter.io>
- _rom_start_addr, _ram_start_addr, _rom_length and _ran_length are
already defined in cortexm_common/Makefile.included and can therefore
be removed from kinetis/Makefile.include
- _ram_base_addr is never used and was not in commit history so
is also removed
- To be able to flash at an offset the vector table must be
relocated accordingly to the IMAGE_OFFSET, therefore linkage
needs to take the offset into account.
Rational: the periph_common module is required by (most) other periph drivers
and also during startup of the CPU/MCU to run periph_init. The latter is only
required if other periph drivers are used, hence periph_common should be a
depency of periph_* modules and *not* of the CPU/MCU. This PR fixes that
by making periph_common a depency of periph_* and removing the explicit
include in the CPU/MCU implementation.
Keep the compiled '.bin' file to remove the need to compile it when
flashing. This remove the need to have the toolchain when flashing so
allow compiling and flashing with `BUILD_IN_DOCKER=1` without a local
toolchain.
Even if it ends up storing a binary, the file is only 34 bytes.
Get OBJDUMP from the environment instead of hardwriting the value.
This is a prerequisite to allow using `objdump` when building from docker
when not having the `arm` toolchain installed.
- fcfield is located in memory at 0x400-0x40f. Its content is only read
upon reset, therefore if in presence of a bootloader and multiple
applications, the fcfield will only be read when the bootloader
is loaded. As long as we flash at IMAGE_OFFSET > 0x410 we do not
care about the fcfield content since it won't get overwritten.
PREFLASHER/PREFFLAGS/FLASHDEPS are evaluated by the main Makefile.include.
Their value does not need to be exported.
Testing
-------
`git diff --word-diff` only reports `export` being removed.
`git show --stat` reports `16 insertions(+), 16 deletions(-)`
Which is the same amount as lines that where matching
`export[[:blank::]]\+VARIABLE` plus the newline that is said to have
changed.
FLASHER and FFLAGS are evaluated by the main Makefile.include or by file
included by it. Their value does not need to be exported.
This will also prevent evaluating 'PORT' for FFLAGS when not needed.
Testing
-------
`git diff --word-diff` only reports `export` being removed.
`git show --stat` reports `84 insertions(+), 84 deletions(-)`
Which is the same amount as lines that where matching
`export[[:blank::]]\+VARIABLE`.
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the same
Timer peripheral, yet each of them carries it's own copy of the Timer
driver.
This introduces a new timer driver that is common for all sam0 MCUs and
uses structs for configuration instead of defines.
If the .noinit section starts at the beginning of the RAM,
a bootloader that is unaware of it will clear it.
Instead, move it behind the .bss section, hoping that a bootloader
will always use less .bss memory than RIOT proper.
This commit adds the periph_uart_mode USEMODULE
It implements all functionality defined in the common uart driver
This means all parity modes, data bits, and stop bits
Make it possible to specify a section of RAM that is not touched by
the init routing so data can be kept across resets.
This should behave the same as on atmega & lpc2387.
gcc9 started realizing that _sram is basically an uint8_t[1] and thus
HARDFAULT_HANDLER_REQUIRED_STACK_SPACE cannot be added to it without
exceeding the one-sized array.
This commit casts _sram to (uintptr_t) where that happens.
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTT
driver.
Unify the drivers and move them to sam0_common.
