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cpu/stm32l0: add support for stm32l052xx
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@ -77,7 +77,7 @@ typedef struct {
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#define EEPROM_START_ADDR (0x08080000)
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#if defined(CPU_LINE_STM32L073xx) || defined(CPU_LINE_STM32L072xx)
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#define EEPROM_SIZE (6144U) /* 6kB */
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#elif defined(CPU_LINE_STM32L053xx)
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#elif defined(CPU_LINE_STM32L053xx) || defined(CPU_LINE_STM32L052xx)
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#define EEPROM_SIZE (2048U) /* 2kB */
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#elif defined(CPU_LINE_STM32L031xx)
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#define EEPROM_SIZE (1024U) /* 1kB */
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7344
cpu/stm32l0/include/vendor/stm32l052xx.h
vendored
Normal file
7344
cpu/stm32l0/include/vendor/stm32l052xx.h
vendored
Normal file
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@ -86,6 +86,15 @@ ISR_VECTOR(1) const isr_t vector_cpu[CPU_IRQ_NUMOF] = {
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#if defined(CPU_LINE_STM32L031xx)
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[ 4] = isr_rcc, /* [ 4] RCC Interrupt */
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[29] = isr_lpuart1, /* [29] LPUART1 Interrupt */
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#elif defined(CPU_LINE_STM32L052xx)
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[ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */
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[ 8] = isr_tsc, /* [ 8] TSC Interrupt */
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[17] = isr_tim6_dac, /* [17] TIM6 and DAC Interrupts */
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[24] = isr_i2c2, /* [24] I2C2 Interrupt */
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[26] = isr_spi2, /* [26] SPI2 Interrupt */
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[27] = isr_usart1, /* [27] USART1 Interrupt */
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[29] = isr_rng_lpuart1, /* [29] RNG and LPUART1 Interrupts */
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[31] = isr_usb, /* [31] USB global Interrupt */
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#elif defined(CPU_LINE_STM32L053xx)
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[ 4] = isr_rcc_crs, /* [ 4] RCC and CRS Interrupts */
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[ 8] = isr_tsc, /* [ 8] TSC Interrupt */
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