Teufelchen1
0e839654e8
cpu/riscv: Add PMP driver
2023-06-28 11:55:34 +02:00
Gunar Schorcht
2ae7566a89
cpu/riscv_common: rename cpu.h to cpu_common.h
...
To allow CPU specific definitions in `cpu.h`, `riscv_common/cpu.h` is renamed to ``riscv_common/cpu_common.h` and included in new `cpu.h` files for FE310 and GD32V.
2023-04-18 06:20:14 +02:00
2eb800cb8b
cpu/fe310: use coreclk instead of cpu_freq
2021-12-15 13:14:19 +01:00
Jan Romann
bd7b277f7e
cpu/fe310: uncrustify
2021-11-18 15:44:17 +01:00
José Alamos
1ee57f80a0
Merge pull request #15030 from jia200x/pr/lora/remove_xtimer
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drivers/sx127x: remove ZTIMER_USEC dependency
2021-09-27 11:41:22 +02:00
f2787448e1
cpu/riscv_common: Move MCAUSE defines to riscv_common
2021-08-24 14:30:23 +02:00
Jose Alamos
94d46e756e
cpu/fe310: fix RTT frequency
2021-07-02 14:53:22 +02:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common
2021-02-05 09:32:19 +01:00
b57b3d490d
cpu/fe310: Allow using immediates for ecall arguments
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The mv instruction (which is usually implemented as `add rd, x0, r1`) is
changed to `add rd, x0, %input`. This can either be used as a load
immediate or as an move.
The code size grows by two bytes. This because GCC does not compress the
li instruction to the compressed version (even though this is possible).
2021-01-22 20:49:52 +01:00
896227ab08
cpu/fe310: Add used registers to clobbers
2021-01-22 20:49:17 +01:00
9979646b8b
cpu/fe310: Inline thread_yield_higher function
2021-01-19 11:03:21 +01:00
ba518ede09
cpu/fe310: Uncrustify code
2021-01-15 12:02:55 +01:00
dc77914ce8
cpu/fe310: add clock configuration header
2020-12-17 15:53:31 +01:00
Marian Buschsieweke
dd48ced151
cpu/*/atomic_utils_arch.h: Add volatile qualifier
2020-11-24 14:00:52 +01:00
792e031a95
Merge pull request #14331 from maribu/atomic_utils
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sys/atomic_utils: Functions for atomic access
2020-11-12 21:44:53 +01:00
Marian Buschsieweke
ce0982485d
cpu/fe310: Add atomic_utils_arch.h
2020-11-10 10:55:13 +01:00
Bas Stottelaar
fb61443bbd
cpu/*: remove unused assert.h include
2020-10-22 11:13:09 +02:00
Marian Buschsieweke
94eab47b26
cpu/fe310: Add architecture_arch.h
2020-09-29 12:34:00 +02:00
Benjamin Valentin
2647f5f3c2
cpu/fe310: run RTT at 1 Hz if RTC is selected
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The RTC on the fe310 is emulated using the RTT.
This only works if the RTT frequency is 1 Hz, so default to that
value in case `periph_rtc` is selected.
2020-09-27 22:45:04 +02:00
ace160a2a3
boards/hifive1: use MHZ utility macro for clock frequency
2020-09-09 14:14:39 +02:00
498646aa17
fe310: Remove vendor plic driver
2020-08-31 16:26:43 +02:00
1d999a1335
fe310: Make header guard unique for plic vendor header
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Otherwise it conflicts with the other plic.h header
2020-08-31 16:26:43 +02:00
3180a11b51
fe310: Add PLIC peripheral driver
2020-08-31 16:26:42 +02:00
Francisco Molina
442b11d0ee
cpu/fe310: add unified rtt configuration
2020-08-12 14:46:59 +02:00
3d9421571c
cpu/fe310: migrate to inlined irq API
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Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
2020-06-26 10:48:56 +02:00
ee3fc27e96
cpu/fe310: implement driver for watchdog
2020-04-07 14:37:55 +02:00
Sören Tempel
bd2f5fe110
fe310: fix power management configuration
2020-01-30 10:43:01 +01:00
Francisco
f76f7c73ce
Merge pull request #12957 from aabadie/pr/cpu/fe310_spi
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cpu/fe310: add spi peripheral driver
2020-01-14 10:54:47 +01:00
Tristan Bruns
532cdc64ff
cpu/fe310: implement SPI
2020-01-11 13:06:39 +01:00
298d573280
cpu/fe310: provide i2c driver
2020-01-11 13:06:10 +01:00
fc911bf6c5
cpu/fe310: rework clock initialization
2020-01-10 16:41:33 +01:00
97e1c7ba7e
cpu/fe310: reorganize files and includes
2020-01-10 16:41:33 +01:00
e5c64c739a
cpu/fe310: rework uart driver implem/config
2019-12-20 15:22:09 +01:00
b49cca2d0c
cpu/fe310: include thread.h in cpu.h
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This ensures the ARRAY_SIZE macro is implicitly available
2019-12-13 16:25:11 +01:00
Marian Buschsieweke
314184adb5
cpu: Platform specific C11 atomics compat headers
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Added headers to define platform specific sizes and types for the C11 atomics
compatibility module for C++.
2019-10-24 23:08:36 +02:00
Kevin "Tristate Tom" Weiss
4b7c5915ec
Merge pull request #10953 from gschorcht/sys/shell/heap_cmd/pr
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sys/shell: add heap command
2019-10-04 13:49:57 +02:00
kenrabold
1d6e37a7f7
cpu/fe310: interrupt handling cleanup
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Cleanup of FE310 interrupt handler code
Optimization of intr context frame
Reduce size of intr stack
Added unhandled trap output
Fix PR #12237
2019-09-27 13:32:43 -07:00
Gunar Schorcht
dfef2ce638
cpu/fe310: changes for common heap command
2019-09-05 09:20:55 +02:00
kenrabold
97d1dc0821
cpu/fe310: Add support for FE310_G002
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Added support for FE310_G002 CPU variant that is on new HiFive1B board
2019-07-19 13:25:17 -07:00
smlng
740eafe93b
cpu/fe310: add missing PERIPH_TIMER_PROVIDES_SET
2018-09-07 22:15:13 +02:00
kenrabold
db4d67c4fd
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY
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Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit
build: fixed missing syscall and cpuid failures
Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph
build: fixed whitespace error
build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY
doc: fixed doxygen warnings
Addressed Doxygen warnings in source file comments
doc: more doxygen fixes
doc: even more doxygen fixes
doc: more changes
build: fix pedantic and rdci_simple build failures
make: exclude lua
2018-05-29 16:27:53 -07:00
kenrabold
7d1d5e77d8
cpu/fe310: add RISC-V cpu FE310
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New CPU FE310 from SiFive based on RISC-V architecture
build: add makefile for RISC-V builds
Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00
