Add support for specifying data bits, stop bits and parity at
runtime.
Introduce feature periph_uart_modecfg for uart_mode() till all
other CPUs implement it.
STM32 L1, F1, F2, F4 supports following modes:
* 7E1, 7E2
* 7O1, 7O2
* 8N1, 8N2
* 8E1, 8E2
* 8O1, 8O2
STM32 L0, L4, F0, F3, F7 supports following modes:
* 6E1, 6E2
* 6O1, 6O2
* 7E1, 7E2
* 7O1, 7O2
* 7N1, 7N2
* 8N1, 8N2
* 8E1, 8E2
* 8O1, 8O2
Use USART_CR1_M1 macro to detect 7-bit support because
even inside one family there could be devices that don't
support 7-bit mode. So just using a family macro is not
enough.
As stated in the datasheets for L0, L4, F0, F3, F7 devices,
data bits can only be changed when UART is disabled (UE=0).
Introduce uart_stop() routine to satisfy this requirement.
STM32 UART adds parity to the MSB of a byte to send. The same
also applies to the received bytes. As a result this bit must
be masked in order to get the pure data.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Refactors i2c_2 to match the structure of i2c_1 better.
Corrects functionality issues.
Allows the common implementation of read_regs and write_regs.
Documents constraints of hardware.
Matches error messages with API.
Now, MCU is able to go in stop mode if necessary when
periph_pm feature is activated.
Regarding LPSDSR bit that deactivates or not regulator in stop
mode, it is up to the user to set/clear this bit. In order
to save power, voltage regulator can be set in low power state
during stop mode but it increases wakeup time.
Signed-off-by: Aurelien Fillau <aurelien.fillau@gmail.com>
* Add support for the STM32 encoder interface
* The STM32 only supports X2 and X4 modes.
* Enable interrupt handler on counter overflow
* Add simple test code for QDEC based on nucleo-f401 board
Signed-off-by: Gilles DOFFE <g.doffe@gmail.com>
Instead of using `weak` function definitions, this PR handles
default implementations using `PROVIDES_x` defines, allowing
for cpus/pm realted modules to use their own implementations.
- removed neccessity to define empty `DAC_NUMOF 0` for each STM
base board
- adapted all board configs to this
- joined stm32f2 to use common DAC driver
- improved code of DAC driver
Implements workaround 1 (use __DSB()) proposed in the stm32 errata
It was possible to lose data when you configure a peripheral
right after enabling its clock
