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cpu/stm32: optimized definition of CPUID_ADDR

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This commit is contained in:
Hauke Petersen 2017-10-13 10:40:35 +02:00
parent 1fec7e690c
commit 5a35517787
59 changed files with 55 additions and 155 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
cpu/stm32_common/include/periph_cpu_common.h
View File

@ -43,16 +43,10 @@ extern "C" {
#error "error: LSI clock speed not defined for your target CPU"
#endif
/**
* @brief Linker script provided symbol for CPUID location
*/
extern uint32_t _cpuid_address;
/**
* @brief Starting offset of CPU_ID
*/
#define CPUID_ADDR (&_cpuid_address)
/**
* @brief Length of the CPU_ID in octets
*
* This is the same for all members of the stm32 family
*/
#define CPUID_LEN (12U)

5
cpu/stm32f0/include/periph_cpu.h
View File

@ -25,6 +25,11 @@
extern "C" {
#endif
/**
* @brief Starting address of the CPU ID
*/
#define CPUID_ADDR (0x1ffff7ac)
/**
* @brief Available ports on the STM32F0 family
*/

3
cpu/stm32f0/ldscripts/stm32f030r8.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f0/ldscripts/stm32f031k6.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 4K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f0/ldscripts/stm32f042k6.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 6K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f0/ldscripts/stm32f051r8.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f0/ldscripts/stm32f070rb.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f0/ldscripts/stm32f072rb.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f0/ldscripts/stm32f091rc.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

5
cpu/stm32f1/include/periph_cpu.h
View File

@ -30,6 +30,11 @@ extern "C" {
*/
#define ADC_DEVS (2U)
/**
* @brief Starting address of the CPU ID
*/
#define CPUID_ADDR (0x1ffff7e8)
/**
* @brief All timers for the STM32F1 have 4 CC channels
*/

3
cpu/stm32f1/ldscripts/stm32f103c8.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f1/ldscripts/stm32f103cb.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f1/ldscripts/stm32f103cb_opencm904.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08003000, LENGTH = 128K-0x3000
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f1/ldscripts/stm32f103cb_sparkcore.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08005000, LENGTH = 128K-0x5000
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f1/ldscripts/stm32f103rb.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f1/ldscripts/stm32f103re.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1ffff7e8, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

5
cpu/stm32f2/include/periph_cpu.h
View File

@ -27,6 +27,11 @@
extern "C" {
#endif
/**
* @brief Starting address of the CPU ID
*/
#define CPUID_ADDR (0x1fff7a10)
/**
* @brief Available ports on the STM32F2 family
*/

3
cpu/stm32f2/ldscripts/stm32f205rg.ld
View File

@ -24,9 +24,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f2/ldscripts/stm32f207zg.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f2/ldscripts/stm32f215rg.ld
View File

@ -24,9 +24,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f2/ldscripts/stm32f215ve.ld
View File

@ -24,9 +24,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f2/ldscripts/stm32f215vg.ld
View File

@ -24,9 +24,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f2/ldscripts/stm32f217zg.ld
View File

@ -24,9 +24,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

5
cpu/stm32f3/include/periph_cpu.h
View File

@ -25,6 +25,11 @@
extern "C" {
#endif
/**
* @brief Starting address of the CPU ID
*/
#define CPUID_ADDR (0x1ffff7ac)
/**
* @brief Available ports on the STM32F3 family
*/

3
cpu/stm32f3/ldscripts/stm32f302r8.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f3/ldscripts/stm32f303k8.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 16K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f3/ldscripts/stm32f303re.ld
View File

@ -25,9 +25,6 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 16K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f3/ldscripts/stm32f303vc.ld
View File

@ -23,9 +23,6 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 40K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 8K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f3/ldscripts/stm32f303ze.ld
View File

@ -23,9 +23,6 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 16K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f3/ldscripts/stm32f334r8.ld
View File

@ -23,9 +23,6 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 12K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 4K
cpuid (r) : ORIGIN = 0x1ffff7ac, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

5
cpu/stm32f4/include/periph_cpu.h
View File

@ -25,6 +25,11 @@
extern "C" {
#endif
/**
* @brief Starting address of the CPU ID
*/
#define CPUID_ADDR (0x1fff7a10)
/**
* @brief Available ports on the STM32F4 family
*/

3
cpu/stm32f4/ldscripts/stm32f401re.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 96K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f407vg.ld
View File

@ -23,9 +23,6 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f410rb.ld
View File

@ -24,9 +24,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 32K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f411re.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f412zg.ld
View File

@ -24,9 +24,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f413vg.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1M
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f413zh.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1536K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f415rg.ld
View File

@ -23,9 +23,6 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f429zi.ld
View File

@ -23,9 +23,6 @@ MEMORY
rom (rx) : ORIGIN = 0x08000000, LENGTH = 2M
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
ccmram (rwx): ORIGIN = 0x10000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f446re.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f4/ldscripts/stm32f446ze.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7a10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

9
cpu/stm32f7/include/periph_cpu.h
View File

@ -27,6 +27,15 @@
extern "C" {
#endif
/**
* @name Starting address of the CPU ID
*/
#ifdef CPU_MODEL_STM32F722ZE
#define CPUID_ADDR (0x1ff07a10)
#else
#define CPUID_ADDR (0x1ff0f420)
#endif
/**
* @brief Available ports
*/

3
cpu/stm32f7/ldscripts/stm32f722ze.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 256K
cpuid (r) : ORIGIN = 0x1ff07A10, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f7/ldscripts/stm32f746zg.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 320K
cpuid (r) : ORIGIN = 0x1ff0f420, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f7/ldscripts/stm32f767zi.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 2M
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 512K
cpuid (r) : ORIGIN = 0x1ff0f420, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32f7/ldscripts/stm32f769ni.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 2048K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 512K
cpuid (r) : ORIGIN = 0x1ff0f420, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

5
cpu/stm32l0/include/periph_cpu.h
View File

@ -28,6 +28,11 @@
extern "C" {
#endif
/**
* @brief Starting address of the CPU ID
*/
#define CPUID_ADDR (0x1ff80050)
/**
* @brief Available ports on the STM32L0 family
*/

3
cpu/stm32l0/ldscripts/stm32l031k6.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 32K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32l0/ldscripts/stm32l053r8.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 64K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32l0/ldscripts/stm32l072cz.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 192K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32l0/ldscripts/stm32l073rz.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 192K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

9
cpu/stm32l1/include/periph_cpu.h
View File

@ -27,6 +27,15 @@
extern "C" {
#endif
/**
* @name Starting address of the CPU ID
*/
#ifdef CPU_MODEL_STM32L151RBA
#define CPUID_ADDR (0x1ff80050)
#else
#define CPUID_ADDR (0x1ff800d0)
#endif
/**
* @brief Available ports on the STM32L1 family
*/

3
cpu/stm32l1/ldscripts/stm32l151rba.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
ram (rw) : ORIGIN = 0x20000000, LENGTH = 32K
cpuid (r) : ORIGIN = 0x1ff80050, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32l1/ldscripts/stm32l151rc.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 32K
cpuid (r) : ORIGIN = 0x1ff800d0, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32l1/ldscripts/stm32l152ret6.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 512K
ram (xrw) : ORIGIN = 0x20000000, LENGTH = 80K
cpuid (r) : ORIGIN = 0x1ff800d0, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

5
cpu/stm32l4/include/periph_cpu.h
View File

@ -26,6 +26,11 @@
extern "C" {
#endif
/**
* @brief Starting address of the CPU ID
*/
#define CPUID_ADDR (0x1fff7590)
/**
* @brief Available ports
*/

3
cpu/stm32l4/ldscripts/stm32l432kc.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 256K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
cpuid (r) : ORIGIN = 0x1fff7590, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld

3
cpu/stm32l4/ldscripts/stm32l476rg.ld
View File

@ -22,9 +22,6 @@ MEMORY
{
rom (rx) : ORIGIN = 0x08000000, LENGTH = 1024K
ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
cpuid (r) : ORIGIN = 0x1fff7590, LENGTH = 12
}
_cpuid_address = ORIGIN(cpuid);
INCLUDE cortexm_base.ld