- fcfield is located in memory at 0x400-0x40f. Its content is only read
upon reset, therefore if in presence of a bootloader and multiple
applications, the fcfield will only be read when the bootloader
is loaded. As long as we flash at IMAGE_OFFSET > 0x410 we do not
care about the fcfield content since it won't get overwritten.
PREFLASHER/PREFFLAGS/FLASHDEPS are evaluated by the main Makefile.include.
Their value does not need to be exported.
Testing
-------
`git diff --word-diff` only reports `export` being removed.
`git show --stat` reports `16 insertions(+), 16 deletions(-)`
Which is the same amount as lines that where matching
`export[[:blank::]]\+VARIABLE` plus the newline that is said to have
changed.
FLASHER and FFLAGS are evaluated by the main Makefile.include or by file
included by it. Their value does not need to be exported.
This will also prevent evaluating 'PORT' for FFLAGS when not needed.
Testing
-------
`git diff --word-diff` only reports `export` being removed.
`git show --stat` reports `84 insertions(+), 84 deletions(-)`
Which is the same amount as lines that where matching
`export[[:blank::]]\+VARIABLE`.
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the same
Timer peripheral, yet each of them carries it's own copy of the Timer
driver.
This introduces a new timer driver that is common for all sam0 MCUs and
uses structs for configuration instead of defines.
If the .noinit section starts at the beginning of the RAM,
a bootloader that is unaware of it will clear it.
Instead, move it behind the .bss section, hoping that a bootloader
will always use less .bss memory than RIOT proper.
This commit adds the periph_uart_mode USEMODULE
It implements all functionality defined in the common uart driver
This means all parity modes, data bits, and stop bits
Make it possible to specify a section of RAM that is not touched by
the init routing so data can be kept across resets.
This should behave the same as on atmega & lpc2387.
gcc9 started realizing that _sram is basically an uint8_t[1] and thus
HARDFAULT_HANDLER_REQUIRED_STACK_SPACE cannot be added to it without
exceeding the one-sized array.
This commit casts _sram to (uintptr_t) where that happens.
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTT
driver.
Unify the drivers and move them to sam0_common.
This removes doing `filter-out periph_hwrng, $(FEATURES_PROVIDED)`
after processing `cpu/$(CPU)/Makefile.features`.
The current solution is a HACK as `CPU_MODEL` is currently not available
at that moment but will be in the near future.
It will allow always including `cpu/$(CPU)/Makefile.features` after
`boards/$(BOARD)/Makefile.features`.
It is a part of moving `CPU/CPU_MODEL` definitions to `Makefile.features`.
UART devices are now configured using static array in header files instead of static variables in implementation to be able to define UART_NUMOF using the size of the array instead of a variable.
SPI devices are now configured using static array in header files instead of static variables in implementation to be able to define SPI_NUMOF using the size of the array instead of a variable.
I2C devices are now configured using static array in header files instead of static variables in implementation to be able to define I2C_NUMOF using the size of the array instead of a variable.
DAC pins are now configured using static arrays in header files instead of static variables in implementation to be able to define DAC_NUMOF using the size of these arrays instead of a variable.
ADC pins are now configured using static arrays in header files instead of static variables in implementation to be able to define ADC_NUMOF using the size of these arrays instead of a variable.
Functions that are used by ADC and DAC peripherals are moved to a new submodule periph_adc_ctrl. This is necessary to compile separate submodules for ADC and DAC.
`top_of_stack` isn't aligned down to the previous 16 byte aligned address. Furthermore, `top_of_stack` as well as `XT_CP_SIZE` are used unaligned in `cpu/esp_common/vendor/xtensa/portasm.S` in the address computation for the coprocessor save area, .
Aligning pointer `p` down to the previous 16 byte aligned address results in a wrong address of the coprocessor save area during the initialization of the thread context. This leads to wrong values and wrong positions of these values in the coprocessor save area in inital thread context.
Since ESP8266 doesn't have a coprocessor, this bug affects only ESP32.
Functions marked with __atribute__((naked)) may only use basic inline assembly
and must not use any c code. The functions __enter_thread_mode() and
cpu_switch_context_exit() are using C code, so they must not be marked as
naked.
Previously the compiler was allowed to reorder access to the interrupt control
registers in regard to memory access not marked as `volatile` (at least some
people - most notably some compiler developers - read the C standard this way).
In practise this did not happen as irq_disable(), irq_restore(), irq_enable()
are part of a separate compilation unit: Calls to external functions unknown to
the compiler are treated as if they were memory barriers. But if link time
optimization (LTO) is enabled, this no longer would work: The compiler could
inline the code accessing the interrupt control registers and reorder the memory
accesses wrapped in irq_disable() and irq_restore() outside of their protection.
This commit adds the "memory" clobber to the inline assembly accessing the
interrupt control registers. This makes those accesses explicit compiler memory
barriers. The machine code generated without LTO enabled should not differ in
any way by this commit. But the use of irq_*() should now be safe with LTO.
During the flash step esptool.py gives the following warning:
WARNING: Flash size arguments in megabits like '16m' are deprecated.
Please use the equivalent size '2MB'.
Megabit arguments may be removed in a future release.
esptool.py v2.7-dev
This patch replaces '16m' with '2MB' to enable future compatibility.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
The currently supported SAM0 MCUs (samd21, saml21, saml1x) share the
same RTC peripheral, yet each of them carries it's own copy of the RTC
driver.
Unify the drivers and move them to sam0_common.
Usually, the access to the IROM (flash) memory requires 32-bit word aligned reads. Attempts to access data in the IROM (flash) memory less than 32 bits in size triggers a LoadStoreError exception. With the exception handler from esp-open-rtos it becomes possible to access data in IROM (flash) with a size of less than 32 bits and thus to place .rodata sections in the IROM (flash).
Fix of #11354: Function '_write_r' of ESP32's newlibc does not write the output of function 'write(STDIO_FILENO, ...)' to the UART interface. To fix this problem, module 'newlib_syscalls_default' is now used by default. Function '_write_r' of module 'newlib_syscalls_default' uses 'stdio_write' which in turn uses 'uart_write' if module 'stdio_uart' is used which is now the default case for ESP32.
This commit cleans up magic number and defines bitfields.
Adds error codes for ADDR/DATA NACK and ARBLOSS
Adds error handling, it corrects when an error occurs
Protects from flags that could lockup the bus
