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Commit Graph

16 Commits

Author SHA1 Message Date
Francisco
3db378e015
Merge pull request #11117 from haukepetersen/add_core_irqisen
core: add irq_is_enabled() function to irq interface
2021-08-26 18:41:02 +02:00
Benjamin Valentin
a75ae3c938 cpu/riscv_common: move C lib selection to common place 2021-08-25 10:53:00 +02:00
Benjamin Valentin
a9c83017ee cpu/riscv_common: only select PLIC for fe310
Not every RISC-V implements that interrupt controller, gd32v uses
CLIC instead.
2021-08-25 10:49:47 +02:00
Hauke Petersen
9a5edcf839 cpu/riscv: implement irq_is_enabled() 2021-08-25 08:01:05 +02:00
benpicco
025770968b
Merge pull request #16036 from bergzand/pr/gd32vf103/initial
gd32v/seeedstudio-gd32: Initial support
2021-08-25 00:38:00 +02:00
f2787448e1 cpu/riscv_common: Move MCAUSE defines to riscv_common 2021-08-24 14:30:23 +02:00
48aa533639
cpu/riscv_common: Add CLIC peripheral driver
The CLIC is a next generation interrupt controller for the RISC-V
architecture.

Co-authored-by:
2021-08-24 10:30:18 +02:00
9239c2fe14
cpu/riscv_common: Add bit set and clear functions 2021-08-24 10:30:15 +02:00
c1d81cfb56
cpu/riscv_common: Jump to rom start on boot
With this the riscv start code jumps to the ROM start on boot when the
ROM area doesn't start at address 0x0.
2021-08-24 10:30:12 +02:00
Jan Romann
4384795cb9
treewide: Remove excessive newlines 2021-08-13 19:50:38 +02:00
Sören Tempel
628c199f51 riscv_common: explicitly mark handle_trap as used
The handle_trap function is used internally by the trap_entry
implementation from the same file. However, the trap_entry
implementation calls handle_trap from inline assembly. This makes it
difficult for the compiler to infer that the handle_trap function is
used at all. This causes issues when LTO is enabled.

Without this patch compiling any RISC-V RIOT code with `LTO=1` causes
the following linker error:

	/home/soeren/src/RIOT/cpu/riscv_common/irq_arch.c:134: undefined reference to `handle_trap'
	/tmp/hello-world.elf.Nngidp.ltrans0.ltrans.o:cpu/riscv_common/irq_arch.c:134:(.text.trap_entry+0x34):
	  relocation truncated to fit: R_RISCV_GPREL_I against undefined symbol `handle_trap'

This commit fixes LTO support for RISC-V.

While at it, also mark the function as static as it is only used by the
trap_entry function from the same compilation unit.
2021-05-05 15:03:12 +02:00
b3b04faadb cpu/fe310: add XFA support 2021-02-18 10:46:08 +01:00
Sören Tempel
5b15dc8932 fe310: Fix debug format strings
read_csr() returns an unsigned long, not a uint32_t. This causes a
-Wformat warning to be emitted when compiling with clang. This commit
fixes the warning by changing the format string.
2020-10-07 19:07:23 +00:00
Sören Tempel
125e4b54c1 fe310: Support the LLVM toolchain (i.e. compilation with clang)
This requires -nostartfiles to be only passed to the linker, not the
compiler, as it is a linker flag and passing it to the compiler causes a
clang warning to be emitted.

Additionally, clang does not seem to support `-mcmodel=medlow` and
`-msmall-data-limit=8` but these options do not seem strictly necessary
to me anyhow thus they are deactivated conditionally when using clang.
2020-10-07 07:37:52 +00:00
0b2810a856
riscv_common: make thread_yield_higher IRQ compatible 2021-02-08 11:04:18 +01:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common 2021-02-05 09:32:19 +01:00