cpu/msp430: reorganize code

RIOT supports two distinct families of the MSP430: The [MSP430 x1xx]
MCU family and the [MSP430 F2xx/G2xx] MCU family. For both incompatible
MCU families the code was located in the msp430fxyz folder, resulting
in case of the UART driver in particularly bizarre code looking roughly
like this:

    #ifndef UART_USE_USCI
    /* implementation of x1xx peripheral ... */
    #else
    /* implementation of F2xx/G2xx peripheral ... */
    #endif
    /* zero shared code between both variants */

This splits the peripheral drivers for USCI and USART serial IP blocks
into separate files and relocates everything in cpu/msp430, similar to
how cpu/stm32 is organized.

[MSP430 x1xx]: https://www.ti.com/lit/ug/slau049f/slau049f.pdf
[MSP430 F2xx/G2xx]: https://www.ti.com/lit/ug/slau144k/slau144k.pdf

boards/common/msb-430/Makefile.features

@@ -1,2 +1,2 @@
-CPU = msp430fxyz
+CPU = msp430
 CPU_MODEL = msp430f1612

boards/msb-430/include/periph_conf.h

@@ -28,12 +28,12 @@
 extern "C" {
 #endif
 
-#define CLOCK_CORECLOCK     msp430_fxyz_dco_freq
+#define CLOCK_CORECLOCK     msp430_dco_freq
 
 /**
  * @brief   Clock configuration
  */
-static const msp430_fxyz_clock_params_t clock_params = {
+static const msp430_clock_params_t clock_params = {
     .target_dco_frequency = 7372800U,
     .lfxt1_frequency = 32768,
     .main_clock_source = MAIN_CLOCK_SOURCE_DCOCLK,

boards/msb-430h/include/periph_conf.h

@@ -32,7 +32,7 @@ extern "C" {
 /**
  * @brief   Clock configuration
  */
-static const msp430_fxyz_clock_params_t clock_params = {
+static const msp430_clock_params_t clock_params = {
     .xt2_frequency = CLOCK_CORECLOCK,
     .lfxt1_frequency = 32768,
     .main_clock_source = MAIN_CLOCK_SOURCE_XT2CLK,

boards/olimex-msp430-h1611/Makefile.features

@@ -1,4 +1,4 @@
-CPU = msp430fxyz
+CPU = msp430
 CPU_MODEL = msp430f1611
 
 # Put defined MCU peripherals here (in alphabetical order)

boards/olimex-msp430-h1611/include/periph_conf.h

@@ -28,12 +28,12 @@
 extern "C" {
 #endif
 
-#define CLOCK_CORECLOCK     msp430_fxyz_dco_freq
+#define CLOCK_CORECLOCK     msp430_dco_freq
 
 /**
  * @brief   Clock configuration
  */
-static const msp430_fxyz_clock_params_t clock_params = {
+static const msp430_clock_params_t clock_params = {
     .target_dco_frequency = MHZ(8),
     .lfxt1_frequency = 32768,
     .main_clock_source = MAIN_CLOCK_SOURCE_DCOCLK,

boards/olimex-msp430-h2618/Makefile.features

@@ -1,4 +1,4 @@
-CPU = msp430fxyz
+CPU = msp430
 CPU_MODEL = msp430f2618
 
 # Put defined MCU peripherals here (in alphabetical order)

boards/olimex-msp430-h2618/include/periph_conf.h

@@ -27,12 +27,12 @@
 extern "C" {
 #endif
 
-#define CLOCK_CORECLOCK     msp430_fxyz_dco_freq
+#define CLOCK_CORECLOCK     msp430_dco_freq
 
 /**
  * @brief   Clock configuration
  */
-static const msp430_fxyz_clock_params_t clock_params = {
+static const msp430_clock_params_t clock_params = {
     .target_dco_frequency = MHZ(16),
     .lfxt1_frequency = 32768,
     .main_clock_source = MAIN_CLOCK_SOURCE_DCOCLK,
@@ -59,7 +59,6 @@ static const msp430_fxyz_clock_params_t clock_params = {
  */
 #define UART_NUMOF          (1U)
 
-#define UART_USE_USCI
 #define UART_BASE           (USCI_0)
 #define UART_IE             (SFR->IE2)
 #define UART_IF             (SFR->IFG2)
@@ -80,7 +79,6 @@ static const msp430_fxyz_clock_params_t clock_params = {
 #define SPI_NUMOF           (1U)
 
 /* SPI configuration */
-#define SPI_USE_USCI
 #define SPI_BASE            (USCI_0_B_SPI)
 #define SPI_IE              (SFR->IE2)
 #define SPI_IF              (SFR->IFG2)

boards/telosb/Makefile.features

@@ -1,4 +1,4 @@
-CPU = msp430fxyz
+CPU = msp430
 CPU_MODEL = msp430f1611
 
 # Put defined MCU peripherals here (in alphabetical order)

boards/telosb/include/periph_conf.h

@@ -28,12 +28,12 @@
 extern "C" {
 #endif
 
-#define CLOCK_CORECLOCK             msp430_fxyz_dco_freq
+#define CLOCK_CORECLOCK             msp430_dco_freq
 
 /**
  * @brief   Clock configuration
  */
-static const msp430_fxyz_clock_params_t clock_params = {
+static const msp430_clock_params_t clock_params = {
     .target_dco_frequency = 2457600U,
     .lfxt1_frequency = 32768,
     .main_clock_source = MAIN_CLOCK_SOURCE_DCOCLK,

boards/z1/Makefile.features

@@ -1,4 +1,4 @@
-CPU = msp430fxyz
+CPU = msp430
 CPU_MODEL = msp430f2617
 
 # Put defined MCU peripherals here (in alphabetical order)

boards/z1/include/periph_conf.h

@@ -28,12 +28,12 @@
 extern "C" {
 #endif
 
-#define CLOCK_CORECLOCK     msp430_fxyz_dco_freq
+#define CLOCK_CORECLOCK     msp430_dco_freq
 
 /**
  * @brief   Clock configuration
  */
-static const msp430_fxyz_clock_params_t clock_params = {
+static const msp430_clock_params_t clock_params = {
     .target_dco_frequency = MHZ(8),
     .lfxt1_frequency = 32768,
     .main_clock_source = MAIN_CLOCK_SOURCE_DCOCLK,
@@ -60,7 +60,6 @@ static const msp430_fxyz_clock_params_t clock_params = {
  */
 #define UART_NUMOF          (1U)
 
-#define UART_USE_USCI
 #define UART_BASE           (USCI_0)
 #define UART_IE             (SFR->IE2)
 #define UART_IF             (SFR->IFG2)
@@ -81,7 +80,6 @@ static const msp430_fxyz_clock_params_t clock_params = {
 #define SPI_NUMOF           (1U)
 
 /* SPI configuration */
-#define SPI_USE_USCI
 #define SPI_BASE            (USCI_0_B_SPI)
 #define SPI_IE              (SFR->IE2)
 #define SPI_IF              (SFR->IFG2)

cpu/msp430/Kconfig

@@ -6,48 +6,42 @@
 # directory for more details.
 #
 
-config MODULE_MSP430_COMMON
+config CPU_ARCH_MSP430
     bool
-    default y if CPU_CORE_MSP430
-    depends on TEST_KCONFIG
     imply MODULE_NEWLIB_NANO
-    select MODULE_MALLOC_THREAD_SAFE
+    select HAS_ARCH_16BIT
-    help
+    select HAS_ARCH_MSP430
-        Common code for MSP430 cores.
+    select HAS_CPU_MSP430
+    select HAS_DBGPIN
+    select HAS_NEWLIB
+    select HAS_PERIPH_FLASHPAGE
+    select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
+    select HAS_PERIPH_FLASHPAGE_PAGEWISE
+    select HAS_PERIPH_PM
+    select MODULE_MALLOC_THREAD_SAFE if TEST_KCONFIG
 
-config MODULE_MSP430_COMMON_PERIPH
+config HAS_CPU_MSP430
     bool
-    default y if CPU_CORE_MSP430
-    depends on TEST_KCONFIG
-    select MODULE_PERIPH
     help
-        Common peripheral code for MSP430 cores.
+        Indicates that an 'MSP430' CPU is being used.
+
+config CPU_MSP430
+    bool
+    select CPU_ARCH_MSP430
 
 choice LIBC_IMPLEMENTATION
     default MODULE_NEWLIB
 endchoice
 
-config CPU_ARCH_MSP430
-    bool
-    select HAS_ARCH_16BIT
-    select HAS_ARCH_MSP430
-    select HAS_DBGPIN
-    select HAS_PERIPH_FLASHPAGE
-    select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
-    select HAS_PERIPH_FLASHPAGE_PAGEWISE
-    select HAS_NEWLIB
-    select HAS_PERIPH_PM
-
-config CPU_CORE_MSP430
-    bool
-    select CPU_ARCH_MSP430
-
 ## Common CPU symbols
 config CPU_ARCH
-    default "msp430" if CPU_ARCH_MSP430
+    default "msp430" if CPU_MSP430
+
+config CPU
+    default "msp430" if CPU_MSP430
 
 config CPU_CORE
-    default "msp430" if CPU_CORE_MSP430
+    default "msp430" if CPU_MSP430
 
 ## Definition of specific features
 config HAS_ARCH_MSP430
@@ -59,3 +53,7 @@ config HAS_ARCH_MSP430
 config GNRC_PKTBUF_SIZE
     default 2560
     depends on KCONFIG_USEMODULE_GNRC_PKTBUF_STATIC
+
+source "$(RIOTCPU)/msp430/periph/Kconfig"
+source "$(RIOTCPU)/msp430/kconfigs/x1xx/Kconfig"
+source "$(RIOTCPU)/msp430/kconfigs/f2xx_g2xx/Kconfig"

cpu/msp430/Makefile

@@ -0,0 +1,5 @@
+MODULE = cpu
+
+DIRS := periph
+
+include $(RIOTBASE)/Makefile.base

cpu/msp430/Makefile.dep

@@ -1,5 +1,4 @@
-USEMODULE += msp430_common
+USEMODULE += newlib
-USEMODULE += msp430_common_periph
 USEMODULE += periph
 
 ifneq (,$(filter newlib,$(USEMODULE)))

cpu/msp430/Makefile.features

@@ -1,8 +1,17 @@
 CPU_ARCH = msp430
 CPU_CORE = msp430
 
+ifneq (,$(filter msp430f2% msp430g2%,$(CPU_MODEL)))
+  CPU_FAM := msp430_f2xx_g2xx
+endif
+
+ifneq (,$(filter msp430f1%,$(CPU_MODEL)))
+  CPU_FAM := msp430_x1xx
+endif
+
 FEATURES_PROVIDED += arch_16bit
 FEATURES_PROVIDED += arch_msp430
+FEATURES_PROVIDED += cpu_$(CPU_FAM)
 FEATURES_PROVIDED += dbgpin
 FEATURES_PROVIDED += newlib
 FEATURES_PROVIDED += periph_flashpage

cpu/msp430/Makefile.include

@@ -1,4 +1,5 @@
-INCLUDES += -I$(RIOTCPU)/msp430_common/include/
+INCLUDES += -I$(RIOTCPU)/msp430/include/
+INCLUDES += -I$(RIOTCPU)/msp430/include/$(subst msp430_,,$(CPU_FAM))
 
 CFLAGS += -DCPU_MODEL_$(call uppercase_and_underscore,$(CPU_MODEL))
 

cpu/msp430/clock.c

@@ -8,7 +8,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430fxyz
+ * @ingroup     cpu_msp430
  * @{
  * @file
  * @brief       MSP430Fxzy clock initialization
@@ -38,9 +38,9 @@
 #define HAS_RSEL3 0
 #endif
 
-uint32_t msp430_fxyz_dco_freq;
+uint32_t msp430_dco_freq;
 
-static inline bool is_dco_in_use(const msp430_fxyz_clock_params_t *params)
+static inline bool is_dco_in_use(const msp430_clock_params_t *params)
 {
     return ((params->main_clock_source == MAIN_CLOCK_SOURCE_DCOCLK) ||
             (params->submain_clock_source == SUBMAIN_CLOCK_SOURCE_DCOCLK));
@@ -253,7 +253,7 @@ static void calibrate_dco(void)
     TACTL = 0;
 
     /* calculate actual DCO frequency */
-    msp430_fxyz_dco_freq = (clock_params.lfxt1_frequency * actual_clock_ratio) >> 3;
+    msp430_dco_freq = (clock_params.lfxt1_frequency * actual_clock_ratio) >> 3;
 }
 
 void default_clock_init(void)
@@ -348,7 +348,7 @@ void default_clock_init(void)
 
 __attribute__((weak, alias("default_clock_init"))) void clock_init(void);
 
-uint32_t msp430_fxyz_submain_clock_freq(void) {
+uint32_t msp430_submain_clock_freq(void) {
     uint16_t shift = (clock_params.submain_clock_divier >> 1) & 0x3;
     switch (clock_params.submain_clock_source) {
     case SUBMAIN_CLOCK_SOURCE_LFXT1CLK:
@@ -361,11 +361,11 @@ uint32_t msp430_fxyz_submain_clock_freq(void) {
         return clock_params.lfxt1_frequency >> shift;
     default:
     case SUBMAIN_CLOCK_SOURCE_DCOCLK:
-        return msp430_fxyz_dco_freq >> shift;
+        return msp430_dco_freq >> shift;
     }
 }
 
-uint32_t msp430_fxyz_auxiliary_clock_freq(void)
+uint32_t msp430_auxiliary_clock_freq(void)
 {
     uint16_t shift = (clock_params.auxiliary_clock_divier >> 4) & 0x3;
     return clock_params.lfxt1_frequency >> shift;

cpu/msp430/doc.txt

@@ -0,0 +1,36 @@
+/**
+@defgroup       cpu_msp430              TI MSP430
+@ingroup        cpu
+@brief          Texas Instruments MSP430 specific code
+
+Support for [TI MSP430] CPU architecture. Check the [MSP430 Dev Guide Book]
+for an overview and a starting point for the CPU architecture. See
+[MSP430 Programming With JTAG] on how to interface with the MCUs.
+
+[TI MSP430]: https://www.ti.com/microcontrollers-mcus-processors/msp430-microcontrollers/overview.html
+[MSP430 Dev Guide Book]: https://www.ti.com/lit/ug/slau840a/slau840a.pdf
+[MSP430 Programming With JTAG]: https://www.ti.com/lit/ug/slau320aj/slau320aj.pdf
+*/
+
+
+/**
+@defgroup        cpu_msp430_f2xx_g2xx   MSP430 F2xx/G2xx MCU family
+@ingroup         cpu_msp430
+@brief           Common code for the MSP430 F2xx/G2xx MCU family
+
+This module contains code common to all of the [MSP430 F2xx/G2xx] MCU family.
+
+[MSP430 F2xx/G2xx]: https://www.ti.com/lit/ug/slau144k/slau144k.pdf
+*/
+
+
+/**
+@defgroup        cpu_msp430_x1xx        MSP430 x1xx MCU family
+@ingroup         cpu_msp430
+@brief           Common code for the MSP430 x1xx MCU family
+
+This module contains code common to all of the [MSP430 x1xx] MCU family.
+
+[MSP430 x1xx]: https://www.ti.com/lit/ug/slau049f/slau049f.pdf
+
+*/

cpu/msp430/include/architecture_arch.h

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430_common
+ * @ingroup     cpu_msp430
  * @{
  *
  * @file

cpu/msp430/include/atomic_utils_arch.h

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430_common
+ * @ingroup     cpu_msp430
  *
  * @{
  *

cpu/msp430/include/cpu.h

@@ -8,8 +8,7 @@
  */
 
 /**
- * @defgroup    cpu_msp430_common TI MSP430
+ * @ingroup     cpu_msp430
- * @ingroup     cpu
  * @brief       Texas Instruments MSP430 specific code
  *
  * @{

cpu/msp430/include/cpu_conf.h

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430_common
+ * @ingroup     cpu_msp430
  * @{
  *
  * @file

cpu/msp430/include/f2xx_g2xx/msp430_regs.h

@@ -0,0 +1,197 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_msp430_f2xx_g2xx
+ * @{
+ *
+ * @file
+ * @brief       Cortex CMSIS style definition of MSP430 registers
+ *
+ * @todo        This file is incomplete, not all registers are listed. Further
+ *              There are probably some inconsistencies throughout the MSP430
+ *              family which need to be addressed.
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef F2XX_G2XX_MSP430_REGS_H
+#define F2XX_G2XX_MSP430_REGS_H
+
+#include <stdint.h>
+
+#include "msp430_regs_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   USCI universal serial control interface registers
+ */
+typedef struct {
+    REG8    ABCTL;      /**< auto baud rate control */
+    REG8    IRTCTL;     /**< IrDA transmit control */
+    REG8    IRRCTL;     /**< IrDA receive control */
+    REG8    ACTL0;      /**< A control 0 */
+    REG8    ACTL1;      /**< A control 1 */
+    REG8    ABR0;       /**< A baud rate control 0 */
+    REG8    ABR1;       /**< A baud rate control 1 */
+    REG8    AMCTL;      /**< A modulation control */
+    REG8    ASTAT;      /**< A status */
+    REG8    ARXBUF;     /**< A receive buffer */
+    REG8    ATXBUF;     /**< A transmit buffer */
+    REG8    BCTL0;      /**< B control 0 */
+    REG8    BCTL1;      /**< B control 1 */
+    REG8    BBR0;       /**< B baud rate 0 */
+    REG8    BBR1;       /**< B baud rate 1 */
+    REG8    BI2CIE;     /**< I2C interrupt enable */
+    REG8    BSTAT;      /**< B status */
+    REG8    BRXBUF;     /**< B receive buffer */
+    REG8    BTXBUF;     /**< B transmit buffer */
+} msp_usci_t;
+
+/**
+ * @brief   USCI SPI specific registers
+ */
+typedef struct {
+    REG8    CTL0;      /**< control 0 */
+    REG8    CTL1;      /**< control 1 */
+    REG8    BR0;       /**< baud rate 0 */
+    REG8    BR1;       /**< baud rate 1 */
+    REG8    reserved;  /**< reserved */
+    REG8    STAT;      /**< status */
+    REG8    RXBUF;     /**< receive buffer */
+    REG8    TXBUF;     /**< transmit buffer */
+} msp_usci_spi_t;
+
+/**
+ * @name    USCI control A register 0 bitmap
+ * @{
+ */
+#define USCI_ACTL0_UCSYNC           (0x01)
+#define USCI_ACTL0_MODE_MASK        (0x06)
+#define USCI_ACTL0_MODE_UART        (0x00)
+#define USCI_ACTL0_MODE_ILMM        (0x02)
+#define USCI_ACTL0_MODE_ABMM        (0x04)
+#define USCI_ACTL0_MODE_UART_ABR    (0x06)
+#define USCI_ACTL0_SPB              (0x08)
+#define USCI_ACTL0_7BIT             (0x10)
+#define USCI_ACTL0_MSB              (0x20)
+#define USCI_ACTL0_PAR              (0x40)
+#define USCI_ACTL0_PEN              (0x80)
+/** @} */
+
+/**
+ * @name    USCI control register 0 bitmap SPI mode
+ * @{
+ */
+#define USCI_SPI_CTL0_UCSYNC        (0x01)
+#define USCI_SPI_CTL0_MODE_3        (0x06)
+#define USCI_SPI_CTL0_MODE_0        (0x00)
+#define USCI_SPI_CTL0_MODE_1        (0x02)
+#define USCI_SPI_CTL0_MODE_2        (0x04)
+#define USCI_SPI_CTL0_MST           (0x08)
+#define USCI_SPI_CTL0_7BIT          (0x10)
+#define USCI_SPI_CTL0_MSB           (0x20)
+#define USCI_SPI_CTL0_CKPL          (0x40)
+#define USCI_SPI_CTL0_CKPH          (0x80)
+/** @} */
+
+/**
+ * @name    USCI status register bitmap SPI mode
+ * @{
+ */
+#define USCI_SPI_STAT_UCBUSY        (0x01)
+#define USCI_SPI_STAT_UCOE          (0x20)
+#define USCI_SPI_STAT_UCFE          (0x40)
+#define USCI_SPI_STAT_UCLISTEN      (0x80)
+/** @} */
+
+/**
+ * @name    USCI control A register 1 bitmap
+ * @{
+ */
+#define USCI_ACTL1_SWRST            (0x01)
+#define USCI_ACTL1_TXBRK            (0x02)
+#define USCI_ACTL1_TXADDR           (0x04)
+#define USCI_ACTL1_DORM             (0x08)
+#define USCI_ACTL1_BRKIE            (0x10)
+#define USCI_ACTL1_RXEIE            (0x20)
+#define USCI_ACTL1_SSEL_MASK        (0xc0)
+#define USCI_ACTL1_SSEL_UCLK        (0x00)
+#define USCI_ACTL1_SSEL_ACLK        (0x40)
+#define USCI_ACTL1_SSEL_SMCLK       (0xc0)
+/** @} */
+
+/**
+ * @name    USCI control register 1 bitmap SPI mode
+ * @{
+ */
+#define USCI_SPI_CTL1_SWRST            (0x01)
+#define USCI_SPI_CTL1_SSEL_MASK        (0xc0)
+#define USCI_SPI_CTL1_SSEL_NA          (0x00)
+#define USCI_SPI_CTL1_SSEL_ACLK        (0x40)
+#define USCI_SPI_CTL1_SSEL_SMCLK       (0xc0)
+/** @} */
+
+/**
+ * @name    USCI modulation A control register
+ * @{
+ */
+#define USCI_AMCTL_OS16             (0x01)
+#define USCI_AMCTL_BRS_MASK         (0xe0)
+#define USCI_AMCTL_BRS_SHIFT        (1U)
+#define USCI_AMCTL_BRF_MASK         (0xf0)
+#define USCI_AMCTL_BRF_SHIFT        (4U)
+/** @} */
+
+/**
+ * @name    USCI status A register bitmap
+ * @{
+ */
+#define USCI_ASTAT_BUSY             (0x01)
+#define USCI_ASTAT_IDLE             (0x02)
+#define USCI_ASTAT_ADDR             (0x02)
+#define USCI_ASTAT_RXERR            (0x04)
+#define USCI_ASTAT_BRK              (0x08)
+#define USCI_ASTAT_PE               (0x10)
+#define USCI_ASTAT_OE               (0x20)
+#define USCI_ASTAT_FE               (0x40)
+#define USCI_ASTAT_LISTEN           (0x80)
+/** @} */
+/**
+ * @name    Base register address definitions
+ * @{
+ */
+#define USCI_0_BASE             ((uint16_t)0x005d)
+#define USCI_0_A_BASE           ((uint16_t)0x0060)
+#define USCI_0_B_BASE           ((uint16_t)0x0068)
+#define USCI_1_BASE             ((uint16_t)0x00cd)
+#define USCI_1_A_BASE           ((uint16_t)0x00d0)
+#define USCI_1_B_BASE           ((uint16_t)0x00d8)
+/** @} */
+
+/**
+ * @name    Typing of base register objects
+ * @{
+ */
+#define USCI_0                  ((msp_usci_t *)USCI_0_BASE)
+#define USCI_1                  ((msp_usci_t *)USCI_1_BASE)
+#define USCI_0_A_SPI            ((msp_usci_spi_t *)USCI_0_A_BASE)
+#define USCI_0_B_SPI            ((msp_usci_spi_t *)USCI_0_B_BASE)
+#define USCI_1_A                ((msp_usci_t *)USCI_1_A_BASE)
+#define USCI_1_B                ((msp_usci_t *)USCI_1_B_BASE)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* F2XX_G2XX_MSP430_REGS_H */
+/** @} */

cpu/msp430/include/f2xx_g2xx/periph_cpu.h

@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_msp430_f2xx_g2xx
+ * @{
+ *
+ * @file
+ * @brief           CPU specific definitions for internal peripheral handling
+ *
+ * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef F2XX_G2XX_PERIPH_CPU_H
+#define F2XX_G2XX_PERIPH_CPU_H
+
+#include <stdbool.h>
+
+#include "periph_cpu_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    Override SPI mode selection values
+ * @{
+ */
+#define HAVE_SPI_MODE_T     /**< MSP430 F2xx/G2xx has a custom spi_mode_t */
+/**
+ * @brief   Support SPI modes
+ */
+typedef enum {
+    SPI_MODE_0 = (USCI_SPI_CTL0_CKPH),                      /**< CPOL=0, CPHA=0 */
+    SPI_MODE_1 = 0,                                         /**< CPOL=0, CPHA=1 */
+    SPI_MODE_2 = (USCI_SPI_CTL0_CKPL | USCI_SPI_CTL0_CKPH), /**< CPOL=1, CPHA=0 */
+    SPI_MODE_3 = (USCI_SPI_CTL0_CKPL)                       /**< CPOL=1, CPHA=1 */
+} spi_mode_t;
+/** @} */
+
+/**
+ * @name    Override SPI clock speed selection values
+ * @{
+ */
+#define HAVE_SPI_CLK_T     /**< MSP430 F2xx/G2xx has a custom spi_clock_t */
+/**
+ * @brief   Support SPI clock frequencies
+ */
+typedef enum {
+    SPI_CLK_100KHZ = 100000,        /**< 100 kHz */
+    SPI_CLK_400KHZ = 400000,        /**< 400 kHz */
+    SPI_CLK_1MHZ   = 1000000,       /**< 1 MHz */
+    SPI_CLK_5MHZ   = 5000000,       /**< 5 MHz */
+    SPI_CLK_10MHZ  = SPI_CLK_5MHZ,  /**< 10 MHz not supported, falling back to 5 MHz */
+} spi_clk_t;
+/** @} */
+
+/**
+ * @name declare needed generic SPI functions
+ * @{
+ */
+#define PERIPH_SPI_NEEDS_INIT_CS        /**< use shared spi_init_cs() */
+#define PERIPH_SPI_NEEDS_TRANSFER_BYTE  /**< use shared spi_transfer_byte() */
+#define PERIPH_SPI_NEEDS_TRANSFER_REG   /**< use shared spi_transfer_reg() */
+#define PERIPH_SPI_NEEDS_TRANSFER_REGS  /**< use shared spi_transfer_regs() */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* F2XX_G2XX_PERIPH_CPU_H */
+/** @} */

cpu/msp430/include/irq_arch.h

@@ -8,7 +8,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430_common
+ * @ingroup     cpu_msp430
 * @{
  *
  * @file

cpu/msp430/include/msp430_regs_common.h

@@ -0,0 +1,238 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_msp430
+ * @{
+ *
+ * @file
+ * @brief       Cortex CMSIS style definition of MSP430 registers
+ *
+ * @todo        This file is incomplete, not all registers are listed. Further
+ *              There are probably some inconsistencies throughout the MSP430
+ *              family which need to be addressed.
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef MSP430_REGS_COMMON_H
+#define MSP430_REGS_COMMON_H
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief   Shortcut to specify 8-bit wide registers
+ */
+#define REG8                volatile uint8_t
+
+/**
+ * @brief   Shortcut to specify 16-bit wide registers
+ */
+#define REG16               volatile uint16_t
+
+/**
+ * @brief   Special function registers
+ */
+typedef struct {
+    REG8    IE1;        /**< interrupt enable 1 */
+    REG8    IE2;        /**< interrupt enable 2 */
+    REG8    IFG1;       /**< interrupt flag 1 */
+    REG8    IFG2;       /**< interrupt flag 2 */
+    REG8    ME1;        /**< module enable 1 */
+    REG8    ME2;        /**< module enable 2 */
+} msp_sfr_t;
+
+/**
+ * @brief   Digital I/O Port w/o interrupt functionality (P3-P6)
+ */
+typedef struct {
+    REG8    IN;         /**< input data */
+    REG8    OD;         /**< output data */
+    REG8    DIR;        /**< pin direction */
+    REG8    SEL;        /**< alternative function select */
+} msp_port_t;
+
+/**
+ * @brief   Digital I/O Port with interrupt functionality (P1 & P2)
+ */
+typedef struct {
+    REG8    IN;         /**< input data */
+    REG8    OD;         /**< output data */
+    REG8    DIR;        /**< pin direction */
+    REG8    IFG;        /**< interrupt flag */
+    REG8    IES;        /**< interrupt edge select */
+    REG8    IE;         /**< interrupt enable */
+    REG8    SEL;        /**< alternative function select */
+} msp_port_isr_t;
+
+/**
+ * @brief   Timer interrupt status registers
+ */
+typedef struct {
+    REG16   TBIV;       /**< TIMER_A interrupt status */
+    REG16   reserved[7];    /**< reserved */
+    REG16   TAIV;       /**< TIMER_B interrupt status */
+} msp_timer_ivec_t;
+
+/**
+ * @brief   Timer module registers
+ */
+typedef struct {
+    REG16   CTL;        /**< timer control */
+    REG16   CCTL[7];    /**< capture compare channel control */
+    REG16   R;          /**< current counter value */
+    REG16   CCR[7];     /**< capture compare channel values */
+} msp_timer_t;
+
+/**
+ * @name    SFR interrupt enable 1 register bitmap
+ * @{
+ */
+#define SFR_IE1_OFIE                (0x02)
+#define SFR_IE1_URXIE0              (0x40)
+#define SFR_IE1_UTXIE0              (0x80)
+/** @} */
+
+/**
+ * @name    SFR interrupt enable 2 register bitmap
+ * @{
+ */
+#define SFR_IE2_UCA0RXIE            (0x01)
+#define SFR_IE2_UCA0TXIE            (0x02)
+#define SFR_IE2_URXIE2              (0x10)
+#define SFR_IE2_UTXIE2              (0x20)
+/** @} */
+
+/**
+ * @name    SFR interrupt flag 1 register bitmap
+ * @{
+ */
+#define SFR_IFG1_OFIFG              (0x02)
+#define SFR_IFG1_URXIFG0            (0x40)
+#define SFR_IFG1_UTXIFG0            (0x80)
+/** @} */
+
+/**
+ * @name    SFR interrupt flag 2 register bitmap
+ * @{
+ */
+#define SFR_IFG2_UCA0RXIFG          (0x01)
+#define SFR_IFG2_UCA0TXIFG          (0x02)
+#define SFR_IFG2_URXIFG1            (0x10)
+#define SFR_IFG2_UTXIFG1            (0x20)
+/** @} */
+
+/**
+ * @name    SFR module enable register 1
+ * @{
+ */
+#define SFR_ME1_USPIE0              (0x40)
+/** @} */
+
+/**
+ * @name    SFR module enable register 2
+ * @{
+ */
+#define SFR_ME2_USPIE1              (0x10)
+/** @} */
+
+/**
+ * @name    Timer Control register bitmap
+ * @{
+ */
+#define TIMER_CTL_IFG                 (0x0001)
+#define TIMER_CTL_IE                  (0x0002)
+#define TIMER_CTL_CLR                 (0x0004)
+#define TIMER_CTL_MC_MASK             (0x0030)
+#define TIMER_CTL_MC_STOP             (0x0000)
+#define TIMER_CTL_MC_UP               (0x0010)
+#define TIMER_CTL_MC_CONT             (0x0020)
+#define TIMER_CTL_MC_UPDOWN           (0x0030)
+#define TIMER_CTL_ID_MASK             (0x00c0)
+#define TIMER_CTL_ID_DIV1             (0x0000)
+#define TIMER_CTL_ID_DIV2             (0x0040)
+#define TIMER_CTL_ID_DIV4             (0x0080)
+#define TIMER_CTL_ID_DIV8             (0x00c0)
+#define TIMER_CTL_TASSEL_MASK         (0x0300)
+#define TIMER_CTL_TASSEL_TCLK         (0x0000)
+#define TIMER_CTL_TASSEL_ACLK         (0x0100)
+#define TIMER_CTL_TASSEL_SMCLK        (0x0200)
+#define TIMER_CTL_TASSEL_INV_TCLK     (0x0300)
+/** @} */
+
+/**
+ * @name    Timer Channel Control register bitmap
+ * @{
+ */
+#define TIMER_CCTL_CCIFG              (0x0001)
+#define TIMER_CCTL_COV                (0x0002)
+#define TIMER_CCTL_OUT                (0x0004)
+#define TIMER_CCTL_CCI                (0x0008)
+#define TIMER_CCTL_CCIE               (0x0010)
+#define TIMER_CCTL_OUTMOD_MASK        (0x00e0)
+#define TIMER_CCTL_OUTMOD_OUTVAL      (0x0000)
+#define TIMER_CCTL_OUTMOD_SET         (0x0020)
+#define TIMER_CCTL_OUTMOD_TOG_RESET   (0x0040)
+#define TIMER_CCTL_OUTMOD_SET_RESET   (0x0060)
+#define TIMER_CCTL_OUTMOD_TOGGLE      (0x0080)
+#define TIMER_CCTL_OUTMOD_RESET       (0x00a0)
+#define TIMER_CCTL_OUTMOD_TOG_SET     (0x00c0)
+#define TIMER_CCTL_OUTMOD_RESET_SET   (0x00e0)
+#define TIMER_CCTL_CAP                (0x0100)
+#define TIMER_CCTL_CLLD_MASK          (0x0600)
+#define TIMER_CCTL_SCS                (0x0800)
+#define TIMER_CCTL_CCIS_MASK          (0x3000)
+#define TIMER_CCTL_CM_MASK            (0xc000)
+/** @} */
+
+/**
+ * @name    Base register address definitions
+ * @{
+ */
+#define SFR_BASE                ((uint16_t)0x0000)
+#define PORT_1_BASE             ((uint16_t)0x0020)
+#define PORT_2_BASE             ((uint16_t)0x0028)
+#define PORT_3_BASE             ((uint16_t)0x0018)
+#define PORT_4_BASE             ((uint16_t)0x001c)
+#define PORT_5_BASE             ((uint16_t)0x0030)
+#define PORT_6_BASE             ((uint16_t)0x0034)
+#define CLK_BASE                ((uint16_t)0x0053)
+#define TIMER_IVEC_BASE         ((uint16_t)0x011e)
+#define TIMER_A_BASE            ((uint16_t)0x0160)
+#define TIMER_B_BASE            ((uint16_t)0x0180)
+#define WD_BASE                 ((uint16_t)0x0120)
+/** @} */
+
+/**
+ * @name    Typing of base register objects
+ * @{
+ */
+#define SFR                     ((msp_sfr_t *)SFR_BASE)
+#define PORT_1                  ((msp_port_t *)PORT_1_BASE)
+#define PORT_2                  ((msp_port_t *)PORT_2_BASE)
+#define PORT_3                  ((msp_port_t *)PORT_3_BASE)
+#define PORT_4                  ((msp_port_t *)PORT_4_BASE)
+#define PORT_5                  ((msp_port_t *)PORT_5_BASE)
+#define PORT_6                  ((msp_port_t *)PORT_6_BASE)
+#define CLK                     ((msp_clk_t *)CLK_BASE)
+#define TIMER_IVEC              ((msp_timer_ivec_t *)TIMER_IVEC_BASE)
+#define TIMER_A                 ((msp_timer_t *)TIMER_A_BASE)
+#define TIMER_B                 ((msp_timer_t *)TIMER_B_BASE)
+#define WD                      ((msp_wd_t *)WD_BASE)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* MSP430_REGS_COMMON_H */
+/** @} */

cpu/msp430/include/periph_cpu_common.h

@@ -7,9 +7,7 @@
  */
 
 /**
- * @defgroup    cpu_msp430fxyz TI MSP430F
+ * @ingroup     cpu_msp430_x1xx
- * @ingroup     cpu
- * @brief       Texas Instruments MSP430F family specific code
  * @{
  *
  * @file
@@ -18,8 +16,8 @@
  * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
  */
 
-#ifndef PERIPH_CPU_H
+#ifndef PERIPH_CPU_COMMON_H
-#define PERIPH_CPU_H
+#define PERIPH_CPU_COMMON_H
 
 #include <stdbool.h>
 
@@ -54,7 +52,6 @@ typedef uint16_t gpio_t;
  */
 #define SPI_HWCS(x)         (SPI_CS_UNDEF)
 
-#ifndef DOXYGEN
 /**
  * @brief   Override flank selection values
  * @{
@@ -67,43 +64,6 @@ typedef enum {
 } gpio_flank_t;
 /** @} */
 
-/**
- * @brief   Override SPI mode selection values
- * @{
- */
-#define HAVE_SPI_MODE_T
-#ifndef SPI_USE_USCI
-typedef enum {
-    SPI_MODE_0 = (USART_TCTL_CKPH),                         /**< CPOL=0, CPHA=0 */
-    SPI_MODE_1 = 0,                                         /**< CPOL=0, CPHA=1 */
-    SPI_MODE_2 = (USART_TCTL_CKPL | USART_TCTL_CKPH),       /**< CPOL=1, CPHA=0 */
-    SPI_MODE_3 = (USART_TCTL_CKPL)                          /**< CPOL=1, CPHA=1 */
-} spi_mode_t;
-#else
-typedef enum {
-    SPI_MODE_0 = (USCI_SPI_CTL0_CKPH),                      /**< CPOL=0, CPHA=0 */
-    SPI_MODE_1 = 0,                                         /**< CPOL=0, CPHA=1 */
-    SPI_MODE_2 = (USCI_SPI_CTL0_CKPL | USCI_SPI_CTL0_CKPH), /**< CPOL=1, CPHA=0 */
-    SPI_MODE_3 = (USCI_SPI_CTL0_CKPL)                       /**< CPOL=1, CPHA=1 */
-} spi_mode_t;
-#endif
-/** @} */
-
-/**
- * @brief   Override SPI clock speed selection values
- * @{
- */
-#define HAVE_SPI_CLK_T
-typedef enum {
-    SPI_CLK_100KHZ = 100000,    /**< 100KHz */
-    SPI_CLK_400KHZ = 400000,    /**< 400KHz */
-    SPI_CLK_1MHZ   = 1000000,   /**< 1MHz */
-    SPI_CLK_5MHZ   = 5000000,   /**< 5MHz */
-    SPI_CLK_10MHZ  = 0,         /**< not supported */
-} spi_clk_t;
-/** @} */
-#endif /* ndef DOXYGEN */
-
 /**
  * @brief   Available ports on MSP430 platforms
  */
@@ -124,23 +84,13 @@ enum {
  */
 void gpio_periph_mode(gpio_t pin, bool enable);
 
-/**
- * @brief declare needed generic SPI functions
- * @{
- */
-#define PERIPH_SPI_NEEDS_INIT_CS
-#define PERIPH_SPI_NEEDS_TRANSFER_BYTE
-#define PERIPH_SPI_NEEDS_TRANSFER_REG
-#define PERIPH_SPI_NEEDS_TRANSFER_REGS
-/** @} */
-
 /**
  * @brief   The measured DCO frequency
  *
  * @warning This will have a value of 0 if the DCO is not enabled in the boards
  *          `periph_conf.h`
  */
-extern uint32_t msp430_fxyz_dco_freq;
+extern uint32_t msp430_dco_freq;
 
 /**
  * @brief   Possible clock sources to generate the main clock from
@@ -163,7 +113,7 @@ typedef enum {
      *          between 450 kHz and 8 MHz
      */
     MAIN_CLOCK_SOURCE_LFXT1CLK     = SELM_3,
-} msp430_fxyz_main_clock_source_t;
+} msp430_main_clock_source_t;
 
 /**
  * @brief   Possible clock sources to generate the submain clock from
@@ -192,7 +142,7 @@ typedef enum {
      * in the config to avoid confusion.
      */
     SUBMAIN_CLOCK_SOURCE_LFXT1CLK      = SELS,
-} msp430_fxyz_submain_clock_source_t;
+} msp430_submain_clock_source_t;
 
 /**
  * @brief   Clock dividers for the main clock
@@ -214,7 +164,7 @@ typedef enum {
      * @brief   Divide the main clock by 8
      */
     MAIN_CLOCK_DIVIDE_BY_8      = DIVM_3,
-} msp430_fxyz_main_clock_divider_t;
+} msp430_main_clock_divider_t;
 
 /**
  * @brief   Clock dividers for the submain clock
@@ -236,7 +186,7 @@ typedef enum {
      * @brief   Divide the main clock by 8
      */
     SUBMAIN_CLOCK_DIVIDE_BY_8   = DIVS_3,
-} msp430_fxyz_submain_clock_divider_t;
+} msp430_submain_clock_divider_t;
 
 /**
  * @brief   Clock dividers for the auxiliary clock
@@ -258,7 +208,7 @@ typedef enum {
      * @brief   Divide the main clock by 8
      */
     AUXILIARY_CLOCK_DIVIDE_BY_8   = DIVA_3,
-} msp430_fxyz_auxiliary_clock_divider_t;
+} msp430_auxiliary_clock_divider_t;
 
 /**
  * @brief   MSP430Fxzy Basic Clock System Parameters
@@ -301,25 +251,25 @@ typedef struct {
      *
      * @details This is the clock the CPU will run at
      */
-    msp430_fxyz_main_clock_source_t main_clock_source;
+    msp430_main_clock_source_t main_clock_source;
     /**
      * @brief   The clock source to select for the submain CPU clock
      *
      * @details This is the clock high speed peripherals will run at
      */
-    msp430_fxyz_submain_clock_source_t submain_clock_source;
+    msp430_submain_clock_source_t submain_clock_source;
     /**
      * @brief   Divider of the main clock
      */
-    msp430_fxyz_main_clock_divider_t main_clock_divier;
+    msp430_main_clock_divider_t main_clock_divier;
     /**
      * @brief   Divider of the submain clock
      */
-    msp430_fxyz_submain_clock_divider_t submain_clock_divier;
+    msp430_submain_clock_divider_t submain_clock_divier;
     /**
      * @brief   Divider of the auxiliary clock
      */
-    msp430_fxyz_auxiliary_clock_divider_t auxiliary_clock_divier;
+    msp430_auxiliary_clock_divider_t auxiliary_clock_divier;
     /**
      * @brief   An external resistor connected to source the current for the DCO
      *
@@ -334,14 +284,14 @@ typedef struct {
      *          XT2IN and XT2OUT
      */
     bool has_xt2;
-} msp430_fxyz_clock_params_t;
+} msp430_clock_params_t;
 
 /**
  * @brief   Initialize the basic clock system to provide the main clock,
  *          the subsystem clock, and the auxiliary clock.
  *
  * The main clock, the subsystem clock, and the auxiliary clock will be set up
- * as specified by `static const msp430_fxyz_clock_params_t clock_params` in
+ * as specified by `static const msp430_clock_params_t clock_params` in
  * the `periph_conf.h` of the board.
  *
  * @note    This function takes some time and typically is only called during
@@ -368,18 +318,18 @@ void clock_init(void);
  *
  * @note    This is only useful when implementing MSP430 peripheral drivers
  */
-uint32_t msp430_fxyz_submain_clock_freq(void);
+uint32_t msp430_submain_clock_freq(void);
 
 /**
  * @brief   Get the configured auxiliary clock frequency
  *
  * @note    This is only useful when implementing MSP430 peripheral drivers
  */
-uint32_t msp430_fxyz_auxiliary_clock_freq(void);
+uint32_t msp430_auxiliary_clock_freq(void);
 
 #ifdef __cplusplus
 }
 #endif
 
-#endif /* PERIPH_CPU_H */
+#endif /* PERIPH_CPU_COMMON_H */
 /** @} */

cpu/msp430/include/thread_arch.h

@@ -8,7 +8,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430_common
+ * @ingroup     cpu_msp430
  * @{
  *
  * @file

cpu/msp430/include/x1xx/msp430_regs.h

@@ -0,0 +1,112 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_msp430_x1xx
+ * @{
+ *
+ * @file
+ * @brief       Cortex CMSIS style definition of MSP430 registers
+ *
+ * @todo        This file is incomplete, not all registers are listed. Further
+ *              There are probably some inconsistencies throughout the MSP430
+ *              family which need to be addressed.
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef X1XX_MSP430_REGS_H
+#define X1XX_MSP430_REGS_H
+
+#include <stdint.h>
+
+#include "msp430_regs_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+/**
+ * @brief   USART (UART, SPI and I2C) registers
+ */
+typedef struct {
+    REG8    CTL;        /**< USART control */
+    REG8    TCTL;       /**< transmit control */
+    REG8    RCTL;       /**< receive control */
+    REG8    MCTL;       /**< modulation control */
+    REG8    BR0;        /**< baud rate control 0 */
+    REG8    BR1;        /**< baud rate control 1 */
+    REG8    RXBUF;      /**< receive buffer */
+    REG8    TXBUF;      /**< transmit buffer */
+} msp_usart_t;
+
+/**
+ * @name    USART control register bitmap
+ * @{
+ */
+#define USART_CTL_SWRST             (0x01)
+#define USART_CTL_MM                (0x02)
+#define USART_CTL_SYNC              (0x04)
+#define USART_CTL_LISTEN            (0x08)
+#define USART_CTL_CHAR              (0x10)
+#define USART_CTL_SPB               (0x20)
+#define USART_CTL_PEV               (0x40)
+#define USART_CTL_PENA              (0x80)
+/** @} */
+
+/**
+ * @name    USART transmit control register bitmap
+ * @{
+ */
+#define USART_TCTL_TXEPT            (0x01)
+#define USART_TCTL_STC              (0x02)
+#define USART_TCTL_TXWAKE           (0x04)
+#define USART_TCTL_URXSE            (0x08)
+#define USART_TCTL_SSEL_MASK        (0x30)
+#define USART_TCTL_SSEL_UCLKI       (0x00)
+#define USART_TCTL_SSEL_ACLK        (0x10)
+#define USART_TCTL_SSEL_SMCLK       (0x20)
+#define USART_TCTL_CKPL             (0x40)
+#define USART_TCTL_CKPH             (0x80)
+/** @} */
+
+/**
+ * @name    USART receive control register bitmap
+ * @{
+ */
+#define USART_RCTL_RXERR            (0x01)
+#define USART_RCTL_RXWAKE           (0x02)
+#define USART_RCTL_URXWIE           (0x04)
+#define USART_RCTL_URXEIE           (0x08)
+#define USART_RCTL_BRK              (0x10)
+#define USART_RCTL_OE               (0x20)
+#define USART_RCTL_PE               (0x40)
+#define USART_RCTL_FE               (0x80)
+/** @} */
+
+/**
+ * @name    Base register address definitions
+ * @{
+ */
+#define USART_0_BASE            ((uint16_t)0x0070)
+#define USART_1_BASE            ((uint16_t)0x0078)
+/** @} */
+
+/**
+ * @name    Typing of base register objects
+ * @{
+ */
+#define USART_0                 ((msp_usart_t *)USART_0_BASE)
+#define USART_1                 ((msp_usart_t *)USART_1_BASE)
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* X1XX_MSP430_REGS_H */
+/** @} */

cpu/msp430/include/x1xx/periph_cpu.h

@@ -0,0 +1,78 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup         cpu_msp430_x1xx
+ * @{
+ *
+ * @file
+ * @brief           CPU specific definitions for internal peripheral handling
+ *
+ * @author          Hauke Petersen <hauke.petersen@fu-berlin.de>
+ */
+
+#ifndef X1XX_PERIPH_CPU_H
+#define X1XX_PERIPH_CPU_H
+
+#include <stdbool.h>
+
+#include "periph_cpu_common.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @name    Override SPI mode selection values
+ * @{
+ */
+#define HAVE_SPI_MODE_T     /**< MSP430 x1xx has a custom spi_mode_t */
+/**
+ * @brief   Supported SPI modes
+ */
+typedef enum {
+    SPI_MODE_0 = (USART_TCTL_CKPH),                     /**< CPOL=0, CPHA=0 */
+    SPI_MODE_1 = 0,                                     /**< CPOL=0, CPHA=1 */
+    SPI_MODE_2 = (USART_TCTL_CKPL | USART_TCTL_CKPH),   /**< CPOL=1, CPHA=0 */
+    SPI_MODE_3 = (USART_TCTL_CKPL)                      /**< CPOL=1, CPHA=1 */
+} spi_mode_t;
+/** @} */
+
+/**
+ * @name    Override SPI clock speed selection values
+ * @{
+ */
+#define HAVE_SPI_CLK_T     /**< MSP430 x1xx has a custom spi_clock_t */
+/**
+ * @brief   Support SPI clock frequencies
+ */
+typedef enum {
+    SPI_CLK_100KHZ = 100000,        /**< 100 kHz */
+    SPI_CLK_400KHZ = 400000,        /**< 400 kHz */
+    SPI_CLK_1MHZ   = 1000000,       /**< 1 MHz */
+    SPI_CLK_5MHZ   = 5000000,       /**< 5 MHz */
+    SPI_CLK_10MHZ  = SPI_CLK_5MHZ,  /**< 10 MHz not supported, falling back to 5 MHz */
+} spi_clk_t;
+/** @} */
+
+/**
+ * @name declare needed generic SPI functions
+ * @{
+ */
+#define PERIPH_SPI_NEEDS_INIT_CS        /**< use shared spi_init_cs() */
+#define PERIPH_SPI_NEEDS_TRANSFER_BYTE  /**< use shared spi_transfer_byte() */
+#define PERIPH_SPI_NEEDS_TRANSFER_REG   /**< use shared spi_transfer_reg() */
+#define PERIPH_SPI_NEEDS_TRANSFER_REGS  /**< use shared spi_transfer_regs() */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* X1XX_PERIPH_CPU_H */
+/** @} */

cpu/msp430/irq.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430_common
+ * @ingroup     cpu_msp430
 * @{
  *
  * @file

cpu/msp430/kconfigs/f2xx_g2xx/Kconfig

@@ -0,0 +1,35 @@
+# Copyright (c) 2020 Freie Universität Berlin
+#               2020 HAW Hamburg
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config CPU_FAM_MSP430_F2XX_G2XX
+    bool
+    select CPU_MSP430
+    select HAS_CPU_MSP430_F2XX_G2XX
+
+## CPU Models
+config CPU_MODEL_MSP430F2617
+    bool
+    select CPU_FAM_MSP430_F2XX_G2XX
+
+config CPU_MODEL_MSP430F2618
+    bool
+    select CPU_FAM_MSP430_F2XX_G2XX
+
+## Definition of specific features
+config HAS_CPU_MSP430_F2XX_G2XX
+    bool
+    help
+        Indicates that an 'MSP430 F2xx/G2xx' CPU is being used.
+
+## Common CPU symbols
+config CPU_FAM
+    default "msp430_f2xx_g2xx" if HAS_CPU_MSP430_F2XX_G2XX
+
+config CPU_MODEL
+    default "msp430f2617" if CPU_MODEL_MSP430F2617
+    default "msp430f2618" if CPU_MODEL_MSP430F2618

cpu/msp430/kconfigs/x1xx/Kconfig

@@ -0,0 +1,35 @@
+# Copyright (c) 2020 Freie Universität Berlin
+#               2020 HAW Hamburg
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config CPU_FAM_MSP430_X1XX
+    bool
+    select CPU_MSP430
+    select HAS_CPU_MSP430_X1XX
+
+## CPU Models
+config CPU_MODEL_MSP430F1611
+    bool
+    select CPU_FAM_MSP430_X1XX
+
+config CPU_MODEL_MSP430F1612
+    bool
+    select CPU_FAM_MSP430_X1XX
+
+## Definition of specific features
+config HAS_CPU_MSP430_X1XX
+    bool
+    help
+        Indicates that an 'MSP430 x1xx' cpu is being used.
+
+## Common CPU symbols
+config CPU_FAM
+    default "msp430_x1xx" if HAS_CPU_MSP430_X1XX
+
+config CPU_MODEL
+    default "msp430f1611" if CPU_MODEL_MSP430F1611
+    default "msp430f1612" if CPU_MODEL_MSP430F1612

cpu/msp430/periph/Kconfig

@@ -0,0 +1,12 @@
+# Copyright (c) 2023 Marian Buschsieweke
+#
+# This file is subject to the terms and conditions of the GNU Lesser
+# General Public License v2.1. See the file LICENSE in the top level
+# directory for more details.
+#
+
+config MODULE_PERIPH
+    bool
+    default y
+    help
+        MSP430 peripheral drivers.

cpu/msp430/periph/Makefile

@@ -0,0 +1,23 @@
+MODULE = periph
+
+# All supported MSP430 families use special serial IP block that implements
+# various serial bus interfaces using the same hardware block. For the
+# MSP430 x1xx family, the block is called USART. For the MSP430 F2xx/G2xx
+# family it is the (incompatible) USCI.
+ifeq (msp430_x1xx,$(CPU_FAM))
+  SERIAL_IP_BLOCK := usart
+endif
+ifeq (msp430_f2xx_g2xx,$(CPU_FAM))
+  SERIAL_IP_BLOCK := usci
+endif
+
+# select family specific peripheral drivers.
+ifneq (,$(filter periph_uart,$(USEMODULE)))
+  SRC += uart_$(SERIAL_IP_BLOCK).c
+endif
+
+ifneq (,$(filter periph_spi,$(USEMODULE)))
+  SRC += spi_$(SERIAL_IP_BLOCK).c
+endif
+
+include $(RIOTMAKE)/periph.mk

cpu/msp430/periph/flashpage.c

@@ -8,7 +8,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430fxyz
+ * @ingroup     cpu_msp430
  * @{
  *
  * @file

cpu/msp430/periph/gpio.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430fxyz
+ * @ingroup     cpu_msp430
  * @ingroup     drivers_periph_gpio
  * @{
  *

cpu/msp430/periph/pm.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430_common
+ * @ingroup     cpu_msp430
  * @ingroup     drivers_periph_pm
  * @{
  *

cpu/msp430/periph/spi_usart.c

@@ -0,0 +1,141 @@
+/*
+ * Copyright (C) 2015-2016 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_msp430_x1xx
+ * @ingroup     drivers_periph_spi
+ * @{
+ *
+ * @file
+ * @brief       Low-level SPI driver implementation
+ *
+ * This SPI driver implementation does only support one single SPI device for
+ * now. This is sufficient, as most MSP430 x1xx CPU's only support two serial
+ * devices - one used as UART and one as SPI.
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include <assert.h>
+
+#include "cpu.h"
+#include "mutex.h"
+#include "periph/spi.h"
+
+/**
+ * @brief   Mutex for locking the SPI device
+ */
+static mutex_t spi_lock = MUTEX_INIT;
+
+void spi_init(spi_t bus)
+{
+    assert((unsigned)bus < SPI_NUMOF);
+
+    /* put SPI device in reset state */
+    SPI_BASE->CTL = USART_CTL_SWRST;
+    SPI_BASE->CTL |= (USART_CTL_CHAR | USART_CTL_SYNC | USART_CTL_MM);
+    SPI_BASE->RCTL = 0;
+    SPI_BASE->MCTL = 0;
+    /* enable SPI mode */
+    SPI_ME |= SPI_ME_BIT;
+
+    /* trigger the pin configuration */
+    spi_init_pins(bus);
+}
+
+void spi_init_pins(spi_t bus)
+{
+    (void)bus;
+
+    gpio_periph_mode(SPI_PIN_MISO, true);
+    gpio_periph_mode(SPI_PIN_MOSI, true);
+    gpio_periph_mode(SPI_PIN_CLK, true);
+}
+
+void spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
+{
+    (void)bus;
+    (void)cs;
+    assert((unsigned)bus < SPI_NUMOF);
+    assert(clk != SPI_CLK_10MHZ);
+
+    /* lock the bus */
+    mutex_lock(&spi_lock);
+
+    /* calculate baudrate */
+    uint32_t br = msp430_submain_clock_freq() / clk;
+    /* make sure the is not smaller then 2 */
+    if (br < 2) {
+        br = 2;
+    }
+    SPI_BASE->BR0 = (uint8_t)br;
+    SPI_BASE->BR1 = (uint8_t)(br >> 8);
+
+    /* configure bus mode */
+    /* configure mode */
+    SPI_BASE->TCTL = (USART_TCTL_SSEL_SMCLK | USART_TCTL_STC | mode);
+    /* release from software reset */
+    SPI_BASE->CTL &= ~(USART_CTL_SWRST);
+}
+
+void spi_release(spi_t bus)
+{
+    (void)bus;
+    /* put SPI device back in reset state */
+    SPI_BASE->CTL |= (USART_CTL_SWRST);
+
+    /* release the bus */
+    mutex_unlock(&spi_lock);
+}
+
+void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
+                        const void *out, void *in, size_t len)
+{
+    (void)bus;
+
+    const uint8_t *out_buf = out;
+    uint8_t *in_buf = in;
+
+    assert(out_buf || in_buf);
+
+    if (cs != SPI_CS_UNDEF) {
+        gpio_clear((gpio_t)cs);
+    }
+
+    /* if we only send out data, we do this the fast way... */
+    if (!in_buf) {
+        for (size_t i = 0; i < len; i++) {
+            while (!(SPI_IF & SPI_IE_TX_BIT)) {}
+            SPI_BASE->TXBUF = out_buf[i];
+        }
+        /* finally we need to wait, until all transfers are complete */
+        while (!(SPI_IF & SPI_IE_TX_BIT) || !(SPI_IF & SPI_IE_RX_BIT)) {}
+        SPI_BASE->RXBUF;
+    }
+    else if (!out_buf) {
+        for (size_t i = 0; i < len; i++) {
+            SPI_BASE->TXBUF = 0;
+            while (!(SPI_IF & SPI_IE_RX_BIT)) {}
+            in_buf[i] = (char)SPI_BASE->RXBUF;
+        }
+    }
+    else {
+        for (size_t i = 0; i < len; i++) {
+            while (!(SPI_IF & SPI_IE_TX_BIT)) {}
+            SPI_BASE->TXBUF = out_buf[i];
+            while (!(SPI_IF & SPI_IE_RX_BIT)) {}
+            in_buf[i] = (char)SPI_BASE->RXBUF;
+        }
+    }
+
+    if ((!cont) && (cs != SPI_CS_UNDEF)) {
+        gpio_set((gpio_t)cs);
+    }
+}

cpu/msp430/periph/spi_usci.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430fxyz
+ * @ingroup     cpu_msp430_f2xx_g2xx
  * @ingroup     drivers_periph_spi
  * @{
  *
@@ -38,20 +38,9 @@ void spi_init(spi_t bus)
 {
     assert((unsigned)bus < SPI_NUMOF);
 
-/* we need to differentiate between the legacy SPI device and USCI */
-#ifndef SPI_USE_USCI
-    /* put SPI device in reset state */
-    SPI_BASE->CTL = USART_CTL_SWRST;
-    SPI_BASE->CTL |= (USART_CTL_CHAR | USART_CTL_SYNC | USART_CTL_MM);
-    SPI_BASE->RCTL = 0;
-    SPI_BASE->MCTL = 0;
-    /* enable SPI mode */
-    SPI_ME |= SPI_ME_BIT;
-#else
     /* reset SPI device */
     SPI_BASE->CTL1 = USCI_SPI_CTL1_SWRST;
     SPI_BASE->CTL1 |= (USCI_SPI_CTL1_SSEL_SMCLK);
-#endif
 
     /* trigger the pin configuration */
     spi_init_pins(bus);
@@ -77,7 +66,7 @@ void spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
     mutex_lock(&spi_lock);
 
     /* calculate baudrate */
-    uint32_t br = msp430_fxyz_submain_clock_freq() / clk;
+    uint32_t br = msp430_submain_clock_freq() / clk;
     /* make sure the is not smaller then 2 */
     if (br < 2) {
         br = 2;
@@ -86,29 +75,18 @@ void spi_acquire(spi_t bus, spi_cs_t cs, spi_mode_t mode, spi_clk_t clk)
     SPI_BASE->BR1 = (uint8_t)(br >> 8);
 
     /* configure bus mode */
-#ifndef SPI_USE_USCI
-    /* configure mode */
-    SPI_BASE->TCTL = (USART_TCTL_SSEL_SMCLK | USART_TCTL_STC | mode);
-    /* release from software reset */
-    SPI_BASE->CTL &= ~(USART_CTL_SWRST);
-#else
     /* configure mode */
     SPI_BASE->CTL0 = (USCI_SPI_CTL0_UCSYNC | USCI_SPI_CTL0_MST|
                      USCI_SPI_CTL0_MODE_0 | USCI_SPI_CTL0_MSB | mode);
     /* release from software reset */
     SPI_BASE->CTL1 &= ~(USCI_SPI_CTL1_SWRST);
-#endif
 }
 
 void spi_release(spi_t bus)
 {
     (void)bus;
     /* put SPI device back in reset state */
-#ifndef SPI_USE_USCI
-    SPI_BASE->CTL |= (USART_CTL_SWRST);
-#else
     SPI_BASE->CTL1 |= (USCI_SPI_CTL1_SWRST);
-#endif
 
     /* release the bus */
     mutex_unlock(&spi_lock);
@@ -135,11 +113,7 @@ void spi_transfer_bytes(spi_t bus, spi_cs_t cs, bool cont,
             SPI_BASE->TXBUF = out_buf[i];
         }
         /* finally we need to wait, until all transfers are complete */
-#ifndef SPI_USE_USCI
-        while (!(SPI_IF & SPI_IE_TX_BIT) || !(SPI_IF & SPI_IE_RX_BIT)) {}
-#else
         while (SPI_BASE->STAT & USCI_SPI_STAT_UCBUSY) {}
-#endif
         SPI_BASE->RXBUF;
     }
     else if (!out_buf) {

cpu/msp430/periph/timer.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430fxyz
+ * @ingroup     cpu_msp430
  * @ingroup     drivers_periph_timer
  * @{
  *

cpu/msp430/periph/uart_usart.c

@@ -7,7 +7,7 @@
  */
 
 /**
- * @ingroup     cpu_msp430fxyz
+ * @ingroup     cpu_msp430_x1xx
  * @ingroup     drivers_periph_uart
  * @{
  *
@@ -34,9 +34,6 @@ static void *ctx_isr_arg;
 
 static int init_base(uart_t uart, uint32_t baudrate);
 
-/* per default, we use the legacy MSP430 USART module for UART functionality */
-#ifndef UART_USE_USCI
-
 int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
 {
     int res = init_base(uart, baudrate);
@@ -72,7 +69,7 @@ static int init_base(uart_t uart, uint32_t baudrate)
     dev->TCTL = (USART_TCTL_TXEPT | USART_TCTL_SSEL_SMCLK);
     dev->RCTL = 0x00;
     /* baudrate configuration */
-    uint16_t br = (uint16_t)(msp430_fxyz_submain_clock_freq() / baudrate);
+    uint16_t br = (uint16_t)(msp430_submain_clock_freq() / baudrate);
     dev->BR0 = (uint8_t)br;
     dev->BR1 = (uint8_t)(br >> 8);
     /* TODO: calculate value for modulation register */
@@ -127,99 +124,3 @@ ISR(UART_RX_ISR, isr_uart_0_rx)
 
     __exit_isr();
 }
-
-/* we use alternative UART code in case the board used the USCI module for UART
- * in case of the (older) USART module */
-#else
-
-int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
-{
-    if (init_base(uart, baudrate) < 0) {
-        return -1;
-    }
-
-    /* save interrupt context */
-    ctx_rx_cb = rx_cb;
-    ctx_isr_arg = arg;
-    /* reset interrupt flags and enable RX interrupt */
-    UART_IF &= ~(UART_IE_RX_BIT);
-    UART_IF |=  (UART_IE_TX_BIT);
-    UART_IE |=  (UART_IE_RX_BIT);
-    UART_IE &= ~(UART_IE_TX_BIT);
-    return 0;
-}
-
-static int init_base(uart_t uart, uint32_t baudrate)
-{
-    if (uart != 0) {
-        return -1;
-    }
-
-    /* get the default UART for now -> TODO: enable for multiple devices */
-    msp_usci_t *dev = UART_BASE;
-
-    /* put device in reset mode while configuration is going on */
-    dev->ACTL1 = USCI_ACTL1_SWRST;
-    /* configure to UART, using SMCLK in 8N1 mode */
-    dev->ACTL1 |= USCI_ACTL1_SSEL_SMCLK;
-    dev->ACTL0 = 0;
-    dev->ASTAT = 0;
-    /* configure baudrate */
-    uint32_t base = ((msp430_fxyz_submain_clock_freq() << 7)  / baudrate);
-    uint16_t br = (uint16_t)(base >> 7);
-    uint8_t brs = (((base & 0x3f) * 8) >> 7);
-    dev->ABR0 = (uint8_t)br;
-    dev->ABR1 = (uint8_t)(br >> 8);
-    dev->AMCTL = (brs << USCI_AMCTL_BRS_SHIFT);
-    /* pin configuration -> TODO: move to GPIO driver once implemented */
-    UART_RX_PORT->SEL |= UART_RX_PIN;
-    UART_TX_PORT->SEL |= UART_TX_PIN;
-    UART_RX_PORT->DIR &= ~(UART_RX_PIN);
-    UART_TX_PORT->DIR |= UART_TX_PIN;
-    /* releasing the software reset bit starts the UART */
-    dev->ACTL1 &= ~(USCI_ACTL1_SWRST);
-    return 0;
-}
-
-void uart_write(uart_t uart, const uint8_t *data, size_t len)
-{
-    (void)uart;
-
-    for (size_t i = 0; i < len; i++) {
-        while (!(UART_IF & UART_IE_TX_BIT)) {}
-        UART_BASE->ATXBUF = data[i];
-    }
-}
-
-void uart_poweron(uart_t uart)
-{
-    (void)uart;
-    /* n/a */
-}
-
-void uart_poweroff(uart_t uart)
-{
-    (void)uart;
-    /* n/a */
-}
-
-ISR(UART_RX_ISR, isr_uart_0_rx)
-{
-    __enter_isr();
-
-    uint8_t stat = UART_BASE->ASTAT;
-    uint8_t data = (uint8_t)UART_BASE->ARXBUF;
-
-    if (stat & (USCI_ASTAT_FE | USCI_ASTAT_OE | USCI_ASTAT_PE | USCI_ASTAT_BRK)) {
-        /* some error which we do not handle, just do a pseudo read to reset the
-         * status register */
-        (void)data;
-    }
-    else {
-        ctx_rx_cb(ctx_isr_arg, data);
-    }
-
-    __exit_isr();
-}
-
-#endif

cpu/msp430/periph/uart_usci.c

@@ -0,0 +1,125 @@
+/*
+ * Copyright (C) 2015 Freie Universität Berlin
+ *
+ * This file is subject to the terms and conditions of the GNU Lesser
+ * General Public License v2.1. See the file LICENSE in the top level
+ * directory for more details.
+ */
+
+/**
+ * @ingroup     cpu_msp430_f2xx_g2xx
+ * @ingroup     drivers_periph_uart
+ * @{
+ *
+ * @file
+ * @brief       Low-level UART driver implementation
+ *
+ * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
+ *
+ * @}
+ */
+
+#include "cpu.h"
+#include "periph_cpu.h"
+#include "periph_conf.h"
+#include "periph/uart.h"
+
+/**
+ * @brief   Keep track of the interrupt context
+ * @{
+ */
+static uart_rx_cb_t ctx_rx_cb;
+static void *ctx_isr_arg;
+/** @} */
+
+static int init_base(uart_t uart, uint32_t baudrate);
+
+int uart_init(uart_t uart, uint32_t baudrate, uart_rx_cb_t rx_cb, void *arg)
+{
+    if (init_base(uart, baudrate) < 0) {
+        return -1;
+    }
+
+    /* save interrupt context */
+    ctx_rx_cb = rx_cb;
+    ctx_isr_arg = arg;
+    /* reset interrupt flags and enable RX interrupt */
+    UART_IF &= ~(UART_IE_RX_BIT);
+    UART_IF |=  (UART_IE_TX_BIT);
+    UART_IE |=  (UART_IE_RX_BIT);
+    UART_IE &= ~(UART_IE_TX_BIT);
+    return 0;
+}
+
+static int init_base(uart_t uart, uint32_t baudrate)
+{
+    if (uart != 0) {
+        return -1;
+    }
+
+    /* get the default UART for now -> TODO: enable for multiple devices */
+    msp_usci_t *dev = UART_BASE;
+
+    /* put device in reset mode while configuration is going on */
+    dev->ACTL1 = USCI_ACTL1_SWRST;
+    /* configure to UART, using SMCLK in 8N1 mode */
+    dev->ACTL1 |= USCI_ACTL1_SSEL_SMCLK;
+    dev->ACTL0 = 0;
+    dev->ASTAT = 0;
+    /* configure baudrate */
+    uint32_t base = ((msp430_submain_clock_freq() << 7)  / baudrate);
+    uint16_t br = (uint16_t)(base >> 7);
+    uint8_t brs = (((base & 0x3f) * 8) >> 7);
+    dev->ABR0 = (uint8_t)br;
+    dev->ABR1 = (uint8_t)(br >> 8);
+    dev->AMCTL = (brs << USCI_AMCTL_BRS_SHIFT);
+    /* pin configuration -> TODO: move to GPIO driver once implemented */
+    UART_RX_PORT->SEL |= UART_RX_PIN;
+    UART_TX_PORT->SEL |= UART_TX_PIN;
+    UART_RX_PORT->DIR &= ~(UART_RX_PIN);
+    UART_TX_PORT->DIR |= UART_TX_PIN;
+    /* releasing the software reset bit starts the UART */
+    dev->ACTL1 &= ~(USCI_ACTL1_SWRST);
+    return 0;
+}
+
+void uart_write(uart_t uart, const uint8_t *data, size_t len)
+{
+    (void)uart;
+
+    for (size_t i = 0; i < len; i++) {
+        while (!(UART_IF & UART_IE_TX_BIT)) {}
+        UART_BASE->ATXBUF = data[i];
+    }
+}
+
+void uart_poweron(uart_t uart)
+{
+    (void)uart;
+    /* n/a */
+}
+
+void uart_poweroff(uart_t uart)
+{
+    (void)uart;
+    /* n/a */
+}
+
+ISR(UART_RX_ISR, isr_uart_0_rx)
+{
+    __enter_isr();
+
+    uint8_t stat = UART_BASE->ASTAT;
+    uint8_t data = (uint8_t)UART_BASE->ARXBUF;
+
+    if (stat & (USCI_ASTAT_FE | USCI_ASTAT_OE | USCI_ASTAT_PE | USCI_ASTAT_BRK)) {
+        /* some error which we do not handle, just do a pseudo read to reset the
+         * status register */
+        (void)data;
+    }
+    else {
+        ctx_rx_cb(ctx_isr_arg, data);
+    }
+
+    __exit_isr();
+}

cpu/msp430_common/Makefile

@@ -1,5 +0,0 @@
-MODULE = msp430_common
-
-DIRS = periph
-
-include $(RIOTBASE)/Makefile.base

cpu/msp430_common/Makefile.default

@@ -1,2 +0,0 @@
-# msp430 uses newlib by default
-DEFAULT_MODULE += newlib

cpu/msp430_common/periph/Makefile

@@ -1,3 +0,0 @@
-MODULE = msp430_common_periph
-
-include $(RIOTMAKE)/periph.mk

cpu/msp430fxyz/Kconfig

@@ -1,50 +0,0 @@
-# Copyright (c) 2020 Freie Universität Berlin
-#               2020 HAW Hamburg
-#
-# This file is subject to the terms and conditions of the GNU Lesser
-# General Public License v2.1. See the file LICENSE in the top level
-# directory for more details.
-#
-
-config CPU_FAM_MSP430F
-    bool
-    select CPU_CORE_MSP430
-    select HAS_CPU_MSP430FXYZ
-
-## CPU Models
-config CPU_MODEL_MSP430F1611
-    bool
-    select CPU_FAM_MSP430F
-
-config CPU_MODEL_MSP430F1612
-    bool
-    select CPU_FAM_MSP430F
-
-config CPU_MODEL_MSP430F2617
-    bool
-    select CPU_FAM_MSP430F
-
-config CPU_MODEL_MSP430F2618
-    bool
-    select CPU_FAM_MSP430F
-
-## Definition of specific features
-config HAS_CPU_MSP430FXYZ
-    bool
-    help
-        Indicates that an 'msp430fxyz' cpu is being used.
-
-## Common CPU symbols
-config CPU_FAM
-    default "msp430f" if CPU_FAM_MSP430F
-
-config CPU_MODEL
-    default "msp430f1611" if CPU_MODEL_MSP430F1611
-    default "msp430f1612" if CPU_MODEL_MSP430F1612
-    default "msp430f2617" if CPU_MODEL_MSP430F2617
-    default "msp430f2618" if CPU_MODEL_MSP430F2618
-
-config CPU
-    default "msp430fxyz" if CPU_FAM_MSP430F
-
-source "$(RIOTCPU)/msp430_common/Kconfig"

cpu/msp430fxyz/Makefile

@@ -1,7 +0,0 @@
-MODULE =cpu
-
-include $(RIOTCPU)/$(CPU)/Makefile.include
-
-DIRS = $(RIOTCPU)/msp430_common periph
-
-include $(RIOTBASE)/Makefile.base

cpu/msp430fxyz/Makefile.default

@@ -1 +0,0 @@
-include $(RIOTCPU)/msp430_common/Makefile.default

cpu/msp430fxyz/Makefile.dep

@@ -1 +0,0 @@
-include $(RIOTCPU)/msp430_common/Makefile.dep

cpu/msp430fxyz/Makefile.features

@@ -1,3 +0,0 @@
-CPU_FAM = msp430f
-
-include $(RIOTCPU)/msp430_common/Makefile.features

cpu/msp430fxyz/Makefile.include

@@ -1 +0,0 @@
-include $(RIOTCPU)/msp430_common/Makefile.include

cpu/msp430fxyz/include/msp430_regs.h

@@ -1,445 +0,0 @@
-/*
- * Copyright (C) 2015 Freie Universität Berlin
- *
- * This file is subject to the terms and conditions of the GNU Lesser
- * General Public License v2.1. See the file LICENSE in the top level
- * directory for more details.
- */
-
-/**
- * @ingroup     cpu_msp430fxyz
- * @{
- *
- * @file
- * @brief       Cortex CMSIS style definition of MSP430 registers
- *
- * @todo        This file is incomplete, not all registers are listed. Further
- *              There are probably some inconsistencies throughout the MSP430
- *              family which need to be addressed.
- *
- * @author      Hauke Petersen <hauke.petersen@fu-berlin.de>
- */
-
-#ifndef MSP430_REGS_H
-#define MSP430_REGS_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * @brief   Shortcut to specify 8-bit wide registers
- */
-#define REG8                volatile uint8_t
-
-/**
- * @brief   Shortcut to specify 16-bit wide registers
- */
-#define REG16               volatile uint16_t
-
-/**
- * @brief   Special function registers
- */
-typedef struct {
-    REG8    IE1;            /**< interrupt enable 1 */
-    REG8    IE2;            /**< interrupt enable 2 */
-    REG8    IFG1;           /**< interrupt flag 1 */
-    REG8    IFG2;           /**< interrupt flag 2 */
-    REG8    ME1;            /**< module enable 1 */
-    REG8    ME2;            /**< module enable 2 */
-} msp_sfr_t;
-
-/**
- * @brief   Digital I/O Port w/o interrupt functionality (P3-P6)
- */
-typedef struct {
-    REG8    IN;         /**< input data */
-    REG8    OD;         /**< output data */
-    REG8    DIR;        /**< pin direction */
-    REG8    SEL;        /**< alternative function select */
-} msp_port_t;
-
-/**
- * @brief   Digital I/O Port with interrupt functionality (P1 & P2)
- */
-typedef struct {
-    REG8    IN;         /**< input data */
-    REG8    OD;         /**< output data */
-    REG8    DIR;        /**< pin direction */
-    REG8    IFG;        /**< interrupt flag */
-    REG8    IES;        /**< interrupt edge select */
-    REG8    IE;         /**< interrupt enable */
-    REG8    SEL;        /**< alternative function select */
-} msp_port_isr_t;
-
-/**
- * @brief   USART (UART, SPI and I2C) registers
- */
-typedef struct {
-    REG8    CTL;        /**< USART control */
-    REG8    TCTL;       /**< transmit control */
-    REG8    RCTL;       /**< receive control */
-    REG8    MCTL;       /**< modulation control */
-    REG8    BR0;        /**< baud rate control 0 */
-    REG8    BR1;        /**< baud rate control 1 */
-    REG8    RXBUF;      /**< receive buffer */
-    REG8    TXBUF;      /**< transmit buffer */
-} msp_usart_t;
-
-/**
- * @brief   USCI universal serial control interface registers
- */
-typedef struct {
-    REG8    ABCTL;      /**< auto baud rate control */
-    REG8    IRTCTL;     /**< IrDA transmit control */
-    REG8    IRRCTL;     /**< IrDA receive control */
-    REG8    ACTL0;      /**< A control 0 */
-    REG8    ACTL1;      /**< A control 1 */
-    REG8    ABR0;       /**< A baud rate control 0 */
-    REG8    ABR1;       /**< A baud rate control 1 */
-    REG8    AMCTL;      /**< A modulation control */
-    REG8    ASTAT;      /**< A status */
-    REG8    ARXBUF;     /**< A receive buffer */
-    REG8    ATXBUF;     /**< A transmit buffer */
-    REG8    BCTL0;      /**< B control 0 */
-    REG8    BCTL1;      /**< B control 1 */
-    REG8    BBR0;       /**< B baud rate 0 */
-    REG8    BBR1;       /**< B baud rate 1 */
-    REG8    BI2CIE;     /**< I2C interrupt enable */
-    REG8    BSTAT;      /**< B status */
-    REG8    BRXBUF;     /**< B receive buffer */
-    REG8    BTXBUF;     /**< B transmit buffer */
-} msp_usci_t;
-
-/**
- * @brief   USCI SPI specific registers
- */
-typedef struct {
-    REG8    CTL0;      /**< control 0 */
-    REG8    CTL1;      /**< control 1 */
-    REG8    BR0;       /**< baud rate 0 */
-    REG8    BR1;       /**< baud rate 1 */
-    REG8    reserved;  /**< reserved */
-    REG8    STAT;      /**< status */
-    REG8    RXBUF;     /**< receive buffer */
-    REG8    TXBUF;     /**< transmit buffer */
-} msp_usci_spi_t;
-
-/**
- * @brief   Timer interrupt status registers
- */
-typedef struct {
-    REG16   TBIV;       /**< TIMER_A interrupt status */
-    REG16   reserved[7];    /**< reserved */
-    REG16   TAIV;       /**< TIMER_B interrupt status */
-} msp_timer_ivec_t;
-
-/**
- * @brief   Timer module registers
- */
-typedef struct {
-    REG16   CTL;        /**< timer control */
-    REG16   CCTL[7];    /**< capture compare channel control */
-    REG16   R;          /**< current counter value */
-    REG16   CCR[7];     /**< capture compare channel values */
-} msp_timer_t;
-
-/**
- * @brief   SFR interrupt enable 1 register bitmap
- * @{
- */
-#define SFR_IE1_OFIE                (0x02)
-#define SFR_IE1_URXIE0              (0x40)
-#define SFR_IE1_UTXIE0              (0x80)
-/** @} */
-
-/**
- * @brief   SFR interrupt enable 2 register bitmap
- * @{
- */
-#define SFR_IE2_UCA0RXIE            (0x01)
-#define SFR_IE2_UCA0TXIE            (0x02)
-#define SFR_IE2_URXIE2              (0x10)
-#define SFR_IE2_UTXIE2              (0x20)
-/** @} */
-
-/**
- * @brief   SFR interrupt flag 1 register bitmap
- * @{
- */
-#define SFR_IFG1_OFIFG              (0x02)
-#define SFR_IFG1_URXIFG0            (0x40)
-#define SFR_IFG1_UTXIFG0            (0x80)
-/** @} */
-
-/**
- * @brief   SFR interrupt flag 2 register bitmap
- * @{
- */
-#define SFR_IFG2_UCA0RXIFG          (0x01)
-#define SFR_IFG2_UCA0TXIFG          (0x02)
-#define SFR_IFG2_URXIFG1            (0x10)
-#define SFR_IFG2_UTXIFG1            (0x20)
-/** @} */
-
-/**
- * @brief   SFR module enable register 1
- * @{
- */
-#define SFR_ME1_USPIE0              (0x40)
-/** @} */
-
-/**
- * @brief   SFR module enable register 2
- * @{
- */
-#define SFR_ME2_USPIE1              (0x10)
-/** @} */
-
-/**
- * @brief   USART control register bitmap
- * @{
- */
-#define USART_CTL_SWRST             (0x01)
-#define USART_CTL_MM                (0x02)
-#define USART_CTL_SYNC              (0x04)
-#define USART_CTL_LISTEN            (0x08)
-#define USART_CTL_CHAR              (0x10)
-#define USART_CTL_SPB               (0x20)
-#define USART_CTL_PEV               (0x40)
-#define USART_CTL_PENA              (0x80)
-/** @} */
-
-/**
- * @brief   USART transmit control register bitmap
- * @{
- */
-#define USART_TCTL_TXEPT            (0x01)
-#define USART_TCTL_STC              (0x02)
-#define USART_TCTL_TXWAKE           (0x04)
-#define USART_TCTL_URXSE            (0x08)
-#define USART_TCTL_SSEL_MASK        (0x30)
-#define USART_TCTL_SSEL_UCLKI       (0x00)
-#define USART_TCTL_SSEL_ACLK        (0x10)
-#define USART_TCTL_SSEL_SMCLK       (0x20)
-#define USART_TCTL_CKPL             (0x40)
-#define USART_TCTL_CKPH             (0x80)
-/** @} */
-
-/**
- * @brief   USART receive control register bitmap
- * @{
- */
-#define USART_RCTL_RXERR            (0x01)
-#define USART_RCTL_RXWAKE           (0x02)
-#define USART_RCTL_URXWIE           (0x04)
-#define USART_RCTL_URXEIE           (0x08)
-#define USART_RCTL_BRK              (0x10)
-#define USART_RCTL_OE               (0x20)
-#define USART_RCTL_PE               (0x40)
-#define USART_RCTL_FE               (0x80)
-/** @} */
-
-/**
- * @brief   USCI control A register 0 bitmap
- * @{
- */
-#define USCI_ACTL0_UCSYNC           (0x01)
-#define USCI_ACTL0_MODE_MASK        (0x06)
-#define USCI_ACTL0_MODE_UART        (0x00)
-#define USCI_ACTL0_MODE_ILMM        (0x02)
-#define USCI_ACTL0_MODE_ABMM        (0x04)
-#define USCI_ACTL0_MODE_UART_ABR    (0x06)
-#define USCI_ACTL0_SPB              (0x08)
-#define USCI_ACTL0_7BIT             (0x10)
-#define USCI_ACTL0_MSB              (0x20)
-#define USCI_ACTL0_PAR              (0x40)
-#define USCI_ACTL0_PEN              (0x80)
-/** @} */
-
-/**
- * @brief   USCI control register 0 bitmap SPI mode
- * @{
- */
-#define USCI_SPI_CTL0_UCSYNC        (0x01)
-#define USCI_SPI_CTL0_MODE_3        (0x06)
-#define USCI_SPI_CTL0_MODE_0        (0x00)
-#define USCI_SPI_CTL0_MODE_1        (0x02)
-#define USCI_SPI_CTL0_MODE_2        (0x04)
-#define USCI_SPI_CTL0_MST           (0x08)
-#define USCI_SPI_CTL0_7BIT          (0x10)
-#define USCI_SPI_CTL0_MSB           (0x20)
-#define USCI_SPI_CTL0_CKPL          (0x40)
-#define USCI_SPI_CTL0_CKPH          (0x80)
-/** @} */
-
-/**
- * @brief   USCI status register bitmap SPI mode
- * @{
- */
-#define USCI_SPI_STAT_UCBUSY        (0x01)
-#define USCI_SPI_STAT_UCOE          (0x20)
-#define USCI_SPI_STAT_UCFE          (0x40)
-#define USCI_SPI_STAT_UCLISTEN      (0x80)
-/** @} */
-
-/**
- * @brief   USCI control A register 1 bitmap
- * @{
- */
-#define USCI_ACTL1_SWRST            (0x01)
-#define USCI_ACTL1_TXBRK            (0x02)
-#define USCI_ACTL1_TXADDR           (0x04)
-#define USCI_ACTL1_DORM             (0x08)
-#define USCI_ACTL1_BRKIE            (0x10)
-#define USCI_ACTL1_RXEIE            (0x20)
-#define USCI_ACTL1_SSEL_MASK        (0xc0)
-#define USCI_ACTL1_SSEL_UCLK        (0x00)
-#define USCI_ACTL1_SSEL_ACLK        (0x40)
-#define USCI_ACTL1_SSEL_SMCLK       (0xc0)
-/** @} */
-
-/**
- * @brief   USCI control register 1 bitmap SPI mode
- * @{
- */
-#define USCI_SPI_CTL1_SWRST            (0x01)
-#define USCI_SPI_CTL1_SSEL_MASK        (0xc0)
-#define USCI_SPI_CTL1_SSEL_NA          (0x00)
-#define USCI_SPI_CTL1_SSEL_ACLK        (0x40)
-#define USCI_SPI_CTL1_SSEL_SMCLK       (0xc0)
-/** @} */
-
-/**
- * @brief   USCI modulation A control register
- * @{
- */
-#define USCI_AMCTL_OS16             (0x01)
-#define USCI_AMCTL_BRS_MASK         (0xe0)
-#define USCI_AMCTL_BRS_SHIFT        (1U)
-#define USCI_AMCTL_BRF_MASK         (0xf0)
-#define USCI_AMCTL_BRF_SHIFT        (4U)
-/** @} */
-
-/**
- * @brief   USCI status A register bitmap
- * @{
- */
-#define USCI_ASTAT_BUSY             (0x01)
-#define USCI_ASTAT_IDLE             (0x02)
-#define USCI_ASTAT_ADDR             (0x02)
-#define USCI_ASTAT_RXERR            (0x04)
-#define USCI_ASTAT_BRK              (0x08)
-#define USCI_ASTAT_PE               (0x10)
-#define USCI_ASTAT_OE               (0x20)
-#define USCI_ASTAT_FE               (0x40)
-#define USCI_ASTAT_LISTEN           (0x80)
-/** @} */
-
-/**
- * @brief   Timer Control register bitmap
- * @{
- */
-#define TIMER_CTL_IFG                 (0x0001)
-#define TIMER_CTL_IE                  (0x0002)
-#define TIMER_CTL_CLR                 (0x0004)
-#define TIMER_CTL_MC_MASK             (0x0030)
-#define TIMER_CTL_MC_STOP             (0x0000)
-#define TIMER_CTL_MC_UP               (0x0010)
-#define TIMER_CTL_MC_CONT             (0x0020)
-#define TIMER_CTL_MC_UPDOWN           (0x0030)
-#define TIMER_CTL_ID_MASK             (0x00c0)
-#define TIMER_CTL_ID_DIV1             (0x0000)
-#define TIMER_CTL_ID_DIV2             (0x0040)
-#define TIMER_CTL_ID_DIV4             (0x0080)
-#define TIMER_CTL_ID_DIV8             (0x00c0)
-#define TIMER_CTL_TASSEL_MASK         (0x0300)
-#define TIMER_CTL_TASSEL_TCLK         (0x0000)
-#define TIMER_CTL_TASSEL_ACLK         (0x0100)
-#define TIMER_CTL_TASSEL_SMCLK        (0x0200)
-#define TIMER_CTL_TASSEL_INV_TCLK     (0x0300)
-/** @} */
-
-/**
- * @brief   Timer Channel Control register bitmap
- * @{
- */
-#define TIMER_CCTL_CCIFG              (0x0001)
-#define TIMER_CCTL_COV                (0x0002)
-#define TIMER_CCTL_OUT                (0x0004)
-#define TIMER_CCTL_CCI                (0x0008)
-#define TIMER_CCTL_CCIE               (0x0010)
-#define TIMER_CCTL_OUTMOD_MASK        (0x00e0)
-#define TIMER_CCTL_OUTMOD_OUTVAL      (0x0000)
-#define TIMER_CCTL_OUTMOD_SET         (0x0020)
-#define TIMER_CCTL_OUTMOD_TOG_RESET   (0x0040)
-#define TIMER_CCTL_OUTMOD_SET_RESET   (0x0060)
-#define TIMER_CCTL_OUTMOD_TOGGLE      (0x0080)
-#define TIMER_CCTL_OUTMOD_RESET       (0x00a0)
-#define TIMER_CCTL_OUTMOD_TOG_SET     (0x00c0)
-#define TIMER_CCTL_OUTMOD_RESET_SET   (0x00e0)
-#define TIMER_CCTL_CAP                (0x0100)
-#define TIMER_CCTL_CLLD_MASK          (0x0600)
-#define TIMER_CCTL_SCS                (0x0800)
-#define TIMER_CCTL_CCIS_MASK          (0x3000)
-#define TIMER_CCTL_CM_MASK            (0xc000)
-/** @} */
-
-/**
- * @brief   Base register address definitions
- * @{
- */
-#define SFR_BASE                ((uint16_t)0x0000)
-#define PORT_1_BASE             ((uint16_t)0x0020)
-#define PORT_2_BASE             ((uint16_t)0x0028)
-#define PORT_3_BASE             ((uint16_t)0x0018)
-#define PORT_4_BASE             ((uint16_t)0x001c)
-#define PORT_5_BASE             ((uint16_t)0x0030)
-#define PORT_6_BASE             ((uint16_t)0x0034)
-#define CLK_BASE                ((uint16_t)0x0053)
-#define USART_0_BASE            ((uint16_t)0x0070)
-#define USART_1_BASE            ((uint16_t)0x0078)
-#define TIMER_IVEC_BASE         ((uint16_t)0x011e)
-#define TIMER_A_BASE            ((uint16_t)0x0160)
-#define TIMER_B_BASE            ((uint16_t)0x0180)
-#define WD_BASE                 ((uint16_t)0x0120)
-#define USCI_0_BASE             ((uint16_t)0x005d)
-#define USCI_0_A_BASE           ((uint16_t)0x0060)
-#define USCI_0_B_BASE           ((uint16_t)0x0068)
-#define USCI_1_BASE             ((uint16_t)0x00cd)
-#define USCI_1_A_BASE           ((uint16_t)0x00d0)
-#define USCI_1_B_BASE           ((uint16_t)0x00d8)
-/** @} */
-
-/**
- * @brief   Typing of base register objects
- * @{
- */
-#define SFR                     ((msp_sfr_t *)SFR_BASE)
-#define PORT_1                  ((msp_port_t *)PORT_1_BASE)
-#define PORT_2                  ((msp_port_t *)PORT_2_BASE)
-#define PORT_3                  ((msp_port_t *)PORT_3_BASE)
-#define PORT_4                  ((msp_port_t *)PORT_4_BASE)
-#define PORT_5                  ((msp_port_t *)PORT_5_BASE)
-#define PORT_6                  ((msp_port_t *)PORT_6_BASE)
-#define CLK                     ((msp_clk_t *)CLK_BASE)
-#define USART_0                 ((msp_usart_t *)USART_0_BASE)
-#define USART_1                 ((msp_usart_t *)USART_1_BASE)
-#define TIMER_IVEC              ((msp_timer_ivec_t *)TIMER_IVEC_BASE)
-#define TIMER_A                 ((msp_timer_t *)TIMER_A_BASE)
-#define TIMER_B                 ((msp_timer_t *)TIMER_B_BASE)
-#define WD                      ((msp_wd_t *)WD_BASE)
-#define USCI_0                  ((msp_usci_t *)USCI_0_BASE)
-#define USCI_1                  ((msp_usci_t *)USCI_1_BASE)
-#define USCI_0_A_SPI            ((msp_usci_spi_t *)USCI_0_A_BASE)
-#define USCI_0_B_SPI            ((msp_usci_spi_t *)USCI_0_B_BASE)
-#define USCI_1_A                ((msp_usci_t *)USCI_1_A_BASE)
-#define USCI_1_B                ((msp_usci_t *)USCI_1_B_BASE)
-/** @} */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* MSP430_REGS_H */
-/** @} */

cpu/msp430fxyz/periph/Makefile

@@ -1 +0,0 @@
-include $(RIOTMAKE)/periph.mk

doc/doxygen/riot.doxyfile

@@ -834,8 +834,8 @@ EXCLUDE_SYMLINKS       = NO
 
 EXCLUDE_PATTERNS       = */board/*/tools/* \
                          */cpu/atmega_common/include/sys/*.h \
-                         */cpu/msp430_common/include/stdatomic.h \
+                         */cpu/msp430/include/stdatomic.h \
-                         */cpu/msp430_common/include/sys/*.h \
+                         */cpu/msp430/include/sys/*.h \
                          */cpu/native/osx-libc-extra \
                          */cpu/x86/include/* \
                          */drivers/kw2xrf/include/overwrites.h \

makefiles/arch/msp430.inc.mk

@@ -2,7 +2,7 @@
 TARGET_ARCH_MSP430 ?= msp430-elf
 TARGET_ARCH ?= $(TARGET_ARCH_MSP430)
 
-MSP430_SUPPORT_FILES ?= $(RIOTCPU)/msp430_common/vendor/msp430-gcc-support-files
+MSP430_SUPPORT_FILES ?= $(RIOTCPU)/msp430/vendor/msp430-gcc-support-files
 
 # define build specific options
 CFLAGS_CPU   = -mmcu=$(CPU_MODEL) -isystem $(MSP430_SUPPORT_FILES)/include
@@ -19,14 +19,14 @@ NEEDS_NEW_LINKER_SCRIPT := $(call version_is_greater_or_equal,$(BINUTILS_VERSION
 LINKFLAGS += $(CFLAGS_CPU) $(CFLAGS_DBG) $(CFLAGS_OPT)
 LINKFLAGS += -Wl,--gc-sections
 LINKFLAGS += -Wl,-L$(MSP430_SUPPORT_FILES)/include
-LINKFLAGS += -Wl,-L$(RIOTCPU)/msp430_common/ldscripts
+LINKFLAGS += -Wl,-L$(RIOTCPU)/msp430/ldscripts
 
 ifeq (1,$(NEEDS_NEW_LINKER_SCRIPT))
   LINKFLAGS += -T riot-$(CPU_MODEL).ld
 else
   LINKFLAGS += -T $(MSP430_SUPPORT_FILES)/include/$(CPU_MODEL).ld
-  LINKFLAGS += -T $(RIOTCPU)/msp430_common/ldscripts/msp430_common.ld
+  LINKFLAGS += -T $(RIOTCPU)/msp430/ldscripts/msp430_common.ld
-  LINKFLAGS += $(RIOTCPU)/msp430_common/ldscripts/xfa.ld
+  LINKFLAGS += $(RIOTCPU)/msp430/ldscripts/xfa.ld
 endif
 
 OPTIONAL_CFLAGS_BLACKLIST += -fdiagnostics-color

sys/include/byteorder.h

@@ -397,15 +397,7 @@ static inline unsigned short __builtin_bswap16(unsigned short a)
 
 static inline uint16_t byteorder_swaps(uint16_t v)
 {
-#ifndef MODULE_MSP430_COMMON
     return __builtin_bswap16(v);
-#else
-    network_uint16_t result = { v };
-    uint8_t tmp = result.u8[0];
-    result.u8[0] = result.u8[1];
-    result.u8[1] = tmp;
-    return result.u16;
-#endif
 }
 
 static inline uint32_t byteorder_swapl(uint32_t v)

sys/newlib_syscalls_default/syscalls.c

@@ -60,7 +60,7 @@
 #define NUM_HEAPS 1
 #endif
 
-#ifdef MODULE_MSP430_COMMON
+#ifdef __MSP430__
 /* the msp430 linker scripts define the end of all memory as __stack, which in
  * turn is used as the initial stack. RIOT also uses __stack as SP on isr
  * entry.  This logic makes __stack - ISR_STACKSIZE the heap end.
@@ -70,7 +70,7 @@ extern char __heap_start__;
 #define _sheap __heap_start__
 #define __eheap (char *)((uintptr_t)&__stack - ISR_STACKSIZE)
 
-#else /* MODULE_MSP430_COMMON */
+#else /* __MSP430__ */
 
 /**
  * @brief manage the heap

tests/pkg/c25519/Makefile

@@ -10,7 +10,7 @@ include $(RIOTBASE)/Makefile.include
 ifneq (,$(filter cortex-%,$(CPU_CORE)))
   CFLAGS += -DTHREAD_STACKSIZE_MAIN=\(THREAD_STACKSIZE_DEFAULT+THREAD_EXTRA_STACKSIZE_PRINTF\)
 else
-ifneq (,$(filter atmega_common msp430_common,$(USEMODULE)))
+ifneq (,$(filter atmega_common msp430,$(USEMODULE)))
   CFLAGS += -DTHREAD_STACKSIZE_MAIN=\(5*THREAD_STACKSIZE_DEFAULT+THREAD_EXTRA_STACKSIZE_PRINTF\)
 else
   CFLAGS += -DTHREAD_STACKSIZE_MAIN=\(3*THREAD_STACKSIZE_DEFAULT+THREAD_EXTRA_STACKSIZE_PRINTF\)