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RIOT supports two distinct families of the MSP430: The [MSP430 x1xx]
MCU family and the [MSP430 F2xx/G2xx] MCU family. For both incompatible
MCU families the code was located in the msp430fxyz folder, resulting
in case of the UART driver in particularly bizarre code looking roughly
like this:
#ifndef UART_USE_USCI
/* implementation of x1xx peripheral ... */
#else
/* implementation of F2xx/G2xx peripheral ... */
#endif
/* zero shared code between both variants */
This splits the peripheral drivers for USCI and USART serial IP blocks
into separate files and relocates everything in cpu/msp430, similar to
how cpu/stm32 is organized.
[MSP430 x1xx]: https://www.ti.com/lit/ug/slau049f/slau049f.pdf
[MSP430 F2xx/G2xx]: https://www.ti.com/lit/ug/slau144k/slau144k.pdf
79 lines
2.1 KiB
C
79 lines
2.1 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_msp430_f2xx_g2xx
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef F2XX_G2XX_PERIPH_CPU_H
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#define F2XX_G2XX_PERIPH_CPU_H
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#include <stdbool.h>
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#include "periph_cpu_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Override SPI mode selection values
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* @{
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*/
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#define HAVE_SPI_MODE_T /**< MSP430 F2xx/G2xx has a custom spi_mode_t */
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/**
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* @brief Support SPI modes
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*/
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typedef enum {
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SPI_MODE_0 = (USCI_SPI_CTL0_CKPH), /**< CPOL=0, CPHA=0 */
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SPI_MODE_1 = 0, /**< CPOL=0, CPHA=1 */
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SPI_MODE_2 = (USCI_SPI_CTL0_CKPL | USCI_SPI_CTL0_CKPH), /**< CPOL=1, CPHA=0 */
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SPI_MODE_3 = (USCI_SPI_CTL0_CKPL) /**< CPOL=1, CPHA=1 */
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} spi_mode_t;
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/** @} */
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/**
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* @name Override SPI clock speed selection values
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* @{
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*/
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#define HAVE_SPI_CLK_T /**< MSP430 F2xx/G2xx has a custom spi_clock_t */
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/**
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* @brief Support SPI clock frequencies
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*/
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typedef enum {
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SPI_CLK_100KHZ = 100000, /**< 100 kHz */
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SPI_CLK_400KHZ = 400000, /**< 400 kHz */
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SPI_CLK_1MHZ = 1000000, /**< 1 MHz */
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SPI_CLK_5MHZ = 5000000, /**< 5 MHz */
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SPI_CLK_10MHZ = SPI_CLK_5MHZ, /**< 10 MHz not supported, falling back to 5 MHz */
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} spi_clk_t;
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/** @} */
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/**
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* @name declare needed generic SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_INIT_CS /**< use shared spi_init_cs() */
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE /**< use shared spi_transfer_byte() */
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#define PERIPH_SPI_NEEDS_TRANSFER_REG /**< use shared spi_transfer_reg() */
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS /**< use shared spi_transfer_regs() */
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* F2XX_G2XX_PERIPH_CPU_H */
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/** @} */
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