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RIOT supports two distinct families of the MSP430: The [MSP430 x1xx]
MCU family and the [MSP430 F2xx/G2xx] MCU family. For both incompatible
MCU families the code was located in the msp430fxyz folder, resulting
in case of the UART driver in particularly bizarre code looking roughly
like this:
#ifndef UART_USE_USCI
/* implementation of x1xx peripheral ... */
#else
/* implementation of F2xx/G2xx peripheral ... */
#endif
/* zero shared code between both variants */
This splits the peripheral drivers for USCI and USART serial IP blocks
into separate files and relocates everything in cpu/msp430, similar to
how cpu/stm32 is organized.
[MSP430 x1xx]: https://www.ti.com/lit/ug/slau049f/slau049f.pdf
[MSP430 F2xx/G2xx]: https://www.ti.com/lit/ug/slau144k/slau144k.pdf
113 lines
3.0 KiB
C
113 lines
3.0 KiB
C
/*
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* Copyright (C) 2015 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup cpu_msp430_x1xx
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* @{
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*
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* @file
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* @brief Cortex CMSIS style definition of MSP430 registers
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*
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* @todo This file is incomplete, not all registers are listed. Further
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* There are probably some inconsistencies throughout the MSP430
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* family which need to be addressed.
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef X1XX_MSP430_REGS_H
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#define X1XX_MSP430_REGS_H
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#include <stdint.h>
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#include "msp430_regs_common.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief USART (UART, SPI and I2C) registers
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*/
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typedef struct {
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REG8 CTL; /**< USART control */
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REG8 TCTL; /**< transmit control */
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REG8 RCTL; /**< receive control */
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REG8 MCTL; /**< modulation control */
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REG8 BR0; /**< baud rate control 0 */
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REG8 BR1; /**< baud rate control 1 */
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REG8 RXBUF; /**< receive buffer */
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REG8 TXBUF; /**< transmit buffer */
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} msp_usart_t;
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/**
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* @name USART control register bitmap
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* @{
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*/
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#define USART_CTL_SWRST (0x01)
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#define USART_CTL_MM (0x02)
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#define USART_CTL_SYNC (0x04)
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#define USART_CTL_LISTEN (0x08)
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#define USART_CTL_CHAR (0x10)
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#define USART_CTL_SPB (0x20)
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#define USART_CTL_PEV (0x40)
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#define USART_CTL_PENA (0x80)
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/** @} */
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/**
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* @name USART transmit control register bitmap
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* @{
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*/
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#define USART_TCTL_TXEPT (0x01)
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#define USART_TCTL_STC (0x02)
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#define USART_TCTL_TXWAKE (0x04)
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#define USART_TCTL_URXSE (0x08)
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#define USART_TCTL_SSEL_MASK (0x30)
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#define USART_TCTL_SSEL_UCLKI (0x00)
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#define USART_TCTL_SSEL_ACLK (0x10)
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#define USART_TCTL_SSEL_SMCLK (0x20)
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#define USART_TCTL_CKPL (0x40)
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#define USART_TCTL_CKPH (0x80)
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/** @} */
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/**
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* @name USART receive control register bitmap
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* @{
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*/
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#define USART_RCTL_RXERR (0x01)
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#define USART_RCTL_RXWAKE (0x02)
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#define USART_RCTL_URXWIE (0x04)
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#define USART_RCTL_URXEIE (0x08)
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#define USART_RCTL_BRK (0x10)
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#define USART_RCTL_OE (0x20)
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#define USART_RCTL_PE (0x40)
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#define USART_RCTL_FE (0x80)
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/** @} */
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/**
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* @name Base register address definitions
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* @{
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*/
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#define USART_0_BASE ((uint16_t)0x0070)
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#define USART_1_BASE ((uint16_t)0x0078)
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/** @} */
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/**
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* @name Typing of base register objects
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* @{
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*/
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#define USART_0 ((msp_usart_t *)USART_0_BASE)
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#define USART_1 ((msp_usart_t *)USART_1_BASE)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* X1XX_MSP430_REGS_H */
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/** @} */
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