2020-06-08 11:25:38 +02:00
|
|
|
# Copyright (c) 2020 HAW Hamburg
|
2022-02-01 22:11:43 +01:00
|
|
|
# 2022 Gunar Schorcht
|
2020-06-08 11:25:38 +02:00
|
|
|
#
|
|
|
|
|
# This file is subject to the terms and conditions of the GNU Lesser
|
|
|
|
|
# General Public License v2.1. See the file LICENSE in the top level
|
|
|
|
|
# directory for more details.
|
|
|
|
|
|
|
|
|
|
## Definition of specific features
|
|
|
|
|
config HAS_ARCH_ESP32
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that the current architecture is any ESP32x SoC architecture.
|
2020-06-08 11:25:38 +02:00
|
|
|
|
|
|
|
|
config HAS_CPU_ESP32
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that the current CPU belongs to the ESP32x SoC series.
|
2020-06-08 11:25:38 +02:00
|
|
|
|
2022-08-11 10:14:56 +02:00
|
|
|
config HAS_ESP_BLE
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Indicates that the used ESP32x SoC supports Bluetooth LE.
|
|
|
|
|
|
|
|
|
|
config HAS_ESP_BLE_ESP32
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Indicates that the ESP32x SoC uses the SDK Bluetooth LE library
|
|
|
|
|
for the ESP32 variant.
|
|
|
|
|
|
2022-08-26 17:10:36 +02:00
|
|
|
config HAS_ESP_BLE_ESP32C3
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Indicates that the ESP32x SoC uses the SDK Bluetooth LE library
|
2022-08-26 18:23:10 +02:00
|
|
|
for the ESP32-C3 or ESP32-S3 variant.
|
2022-08-26 17:10:36 +02:00
|
|
|
|
2022-06-18 18:57:19 +02:00
|
|
|
config HAS_ESP_HW_COUNTER
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that the used ESP32x SoC supports HW counters that can be
|
|
|
|
|
used as timers.
|
2022-06-18 18:57:19 +02:00
|
|
|
|
2023-03-26 18:30:37 +02:00
|
|
|
config HAS_ESP_RMT
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Indicates that the ESP32x SoC has a RMT peripheral.
|
|
|
|
|
|
2020-06-08 11:25:38 +02:00
|
|
|
config HAS_ESP_RTC_TIMER_32K
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that an external 32.768 kHz crystal is connected to the
|
|
|
|
|
ESP32x Soc on the board.
|
2020-06-08 11:25:38 +02:00
|
|
|
|
|
|
|
|
config HAS_ESP_SPI_RAM
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that an external RAM is connected via the SPI interface to
|
|
|
|
|
the ESP32x SoC on the board.
|
2020-06-08 11:25:38 +02:00
|
|
|
|
2022-07-22 13:52:29 +02:00
|
|
|
config HAS_ESP_SPI_OCT
|
|
|
|
|
bool
|
|
|
|
|
help
|
|
|
|
|
Indicates that Octal SPI mode is used for Flash and SPI RAM. In this
|
|
|
|
|
case additional GPIOs are used for the SPI interface and cannot be
|
|
|
|
|
used for other purposes.
|
|
|
|
|
|
2020-06-08 11:25:38 +02:00
|
|
|
config CPU
|
2022-07-18 16:10:08 +02:00
|
|
|
default "esp32" if HAS_CPU_ESP32
|
2022-07-18 09:52:26 +02:00
|
|
|
|
2022-08-24 17:15:37 +02:00
|
|
|
config CPU_CORE_XTENSA_LX6
|
|
|
|
|
bool
|
|
|
|
|
select CPU_ARCH_XTENSA
|
|
|
|
|
help
|
|
|
|
|
CPU core of the ESP32x SoC is a Xtensa LX6.
|
|
|
|
|
|
|
|
|
|
config CPU_CORE_XTENSA_LX7
|
|
|
|
|
bool
|
|
|
|
|
select CPU_ARCH_XTENSA
|
|
|
|
|
help
|
|
|
|
|
CPU core of the ESP32x SoC is a Xtensa LX7.
|
|
|
|
|
|
|
|
|
|
config CPU_CORE_RV32IMC
|
|
|
|
|
bool
|
|
|
|
|
select CPU_ARCH_RISCV
|
|
|
|
|
help
|
|
|
|
|
CPU core of the ESP32x SoC is a RISC-V core.
|
|
|
|
|
|
|
|
|
|
config CPU_CORE
|
|
|
|
|
default "xtensa-lx6" if CPU_CORE_XTENSA_LX6
|
|
|
|
|
default "xtensa-lx7" if CPU_CORE_XTENSA_LX7
|
|
|
|
|
default "rv32imc" if CPU_CORE_RV32IMC
|
|
|
|
|
|
2023-03-30 07:34:02 +02:00
|
|
|
rsource "Kconfig.esp32x"
|
2022-07-18 16:10:08 +02:00
|
|
|
rsource "Kconfig.esp32"
|
2022-07-20 06:55:58 +02:00
|
|
|
rsource "Kconfig.esp32c3"
|
2022-07-22 13:52:29 +02:00
|
|
|
rsource "Kconfig.esp32s3"
|
2022-07-31 11:48:53 +02:00
|
|
|
rsource "Kconfig.esp32s2"
|
2023-04-05 14:58:36 +02:00
|
|
|
rsource "stdio_usb_serial_jtag/Kconfig"
|
2021-11-18 17:17:04 +01:00
|
|
|
|
2020-06-08 11:25:38 +02:00
|
|
|
source "$(RIOTCPU)/esp_common/Kconfig"
|
