2020-06-08 11:25:38 +02:00
|
|
|
# Copyright (c) 2020 HAW Hamburg
|
2022-02-01 22:11:43 +01:00
|
|
|
# 2022 Gunar Schorcht
|
2020-06-08 11:25:38 +02:00
|
|
|
#
|
|
|
|
|
# This file is subject to the terms and conditions of the GNU Lesser
|
|
|
|
|
# General Public License v2.1. See the file LICENSE in the top level
|
|
|
|
|
# directory for more details.
|
|
|
|
|
|
|
|
|
|
## Definition of specific features
|
|
|
|
|
config HAS_ARCH_ESP32
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that the current architecture is any ESP32x SoC architecture.
|
2020-06-08 11:25:38 +02:00
|
|
|
|
|
|
|
|
config HAS_CPU_ESP32
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that the current CPU belongs to the ESP32x SoC series.
|
2020-06-08 11:25:38 +02:00
|
|
|
|
2022-06-18 18:57:19 +02:00
|
|
|
config HAS_ESP_HW_COUNTER
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that the used ESP32x SoC supports HW counters that can be
|
|
|
|
|
used as timers.
|
2022-06-18 18:57:19 +02:00
|
|
|
|
2020-06-08 11:25:38 +02:00
|
|
|
config HAS_ESP_RTC_TIMER_32K
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that an external 32.768 kHz crystal is connected to the
|
|
|
|
|
ESP32x Soc on the board.
|
2020-06-08 11:25:38 +02:00
|
|
|
|
|
|
|
|
config HAS_ESP_SPI_RAM
|
|
|
|
|
bool
|
|
|
|
|
help
|
2022-07-18 16:10:08 +02:00
|
|
|
Indicates that an external RAM is connected via the SPI interface to
|
|
|
|
|
the ESP32x SoC on the board.
|
2020-06-08 11:25:38 +02:00
|
|
|
|
|
|
|
|
config CPU
|
2022-07-18 16:10:08 +02:00
|
|
|
default "esp32" if HAS_CPU_ESP32
|
2022-07-18 09:52:26 +02:00
|
|
|
|
2022-07-18 16:10:08 +02:00
|
|
|
rsource "Kconfig.esp32"
|
2022-07-20 06:55:58 +02:00
|
|
|
rsource "Kconfig.esp32c3"
|
2021-11-18 17:17:04 +01:00
|
|
|
|
2020-06-08 11:25:38 +02:00
|
|
|
source "$(RIOTCPU)/esp_common/Kconfig"
|
