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cpu/esp*: cleanup of CPU_ARCH* and CPU_CORE*

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This commit is contained in:
Gunar Schorcht 2022-08-24 17:15:37 +02:00
parent 13e3e09414
commit 8ee714cc9b
6 changed files with 34 additions and 41 deletions
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23
cpu/esp32/Kconfig
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@ -44,6 +44,29 @@ config HAS_ESP_SPI_OCT
config CPU
default "esp32" if HAS_CPU_ESP32
config CPU_CORE_XTENSA_LX6
bool
select CPU_ARCH_XTENSA
help
CPU core of the ESP32x SoC is a Xtensa LX6.
config CPU_CORE_XTENSA_LX7
bool
select CPU_ARCH_XTENSA
help
CPU core of the ESP32x SoC is a Xtensa LX7.
config CPU_CORE_RV32IMC
bool
select CPU_ARCH_RISCV
help
CPU core of the ESP32x SoC is a RISC-V core.
config CPU_CORE
default "xtensa-lx6" if CPU_CORE_XTENSA_LX6
default "xtensa-lx7" if CPU_CORE_XTENSA_LX7
default "rv32imc" if CPU_CORE_RV32IMC
rsource "Kconfig.esp32"
rsource "Kconfig.esp32c3"
rsource "Kconfig.esp32s3"

7
cpu/esp32/Kconfig.esp32
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@ -5,13 +5,6 @@
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config CPU_CORE_XTENSA_LX6
bool
select CPU_ARCH_XTENSA
config CPU_CORE
default "xtensa-lx6" if CPU_CORE_XTENSA_LX6
config CPU_FAM_ESP32
bool
select CPU_COMMON_ESP

20
cpu/esp32/Kconfig.esp32c3
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@ -5,26 +5,6 @@
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config CPU_ARCH_RISCV
bool
select HAS_ARCH_32BIT
select HAS_ARCH_ESP
select HAS_ARCH_ESP_RISCV
help
RISC-V based ESP32x SoC variant is used.
config CPU_ARCH
default "rv32" if CPU_ARCH_RISCV
config CPU_CORE_RV32IMC
bool
select CPU_ARCH_RISCV
help
CPU core of the ESP32x SoC is a RISC-V core.
config CPU_CORE
default "rv32imc" if CPU_CORE_RV32IMC
config CPU_FAM_ESP32C3
bool
select CPU_COMMON_ESP

7
cpu/esp32/Kconfig.esp32s2
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@ -5,13 +5,6 @@
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config CPU_CORE_XTENSA_LX7
bool
select CPU_ARCH_XTENSA
config CPU_CORE
default "xtensa-lx7" if CPU_CORE_XTENSA_LX7
config CPU_FAM_ESP32S2
bool
select CPU_COMMON_ESP

7
cpu/esp32/Kconfig.esp32s3
View File

@ -5,13 +5,6 @@
# General Public License v2.1. See the file LICENSE in the top level
# directory for more details.
config CPU_CORE_XTENSA_LX7
bool
select CPU_ARCH_XTENSA
config CPU_CORE
default "xtensa-lx7" if CPU_CORE_XTENSA_LX7
config CPU_FAM_ESP32S3
bool
select CPU_COMMON_ESP

11
cpu/esp_common/Kconfig
View File

@ -9,6 +9,16 @@ config CPU_ARCH_XTENSA
select HAS_ARCH_32BIT
select HAS_ARCH_ESP
select HAS_ARCH_ESP_XTENSA
help
Xtensa based architecture is used for the ESP8266 or the ESP32x SoC variant
config CPU_ARCH_RISCV
bool
select HAS_ARCH_32BIT
select HAS_ARCH_ESP
select HAS_ARCH_ESP_RISCV
help
RISC-V based architecture is used for the ESP32x SoC variant.
config CPU_COMMON_ESP
bool
@ -83,6 +93,7 @@ config HAS_ESP_WIFI_ENTERPRISE
## Common CPU symbols
config CPU_ARCH
default "xtensa" if CPU_ARCH_XTENSA
default "rv32" if CPU_ARCH_RISCV
config MODULE_ESP_COMMON
bool