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934028c114
RIOT/cpu/stm32/include/clk/l4l5wb
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Alexandre Abadie 934028c114
cpu/stm32: fix l4l5wb clock configuration 
Default values were wrong for WB when using HSE 32MHz as PLL input source
Default PLL input source was wrong when not using HSE and the board
provides an HSE
2020-11-10 09:34:07 +01:00
..
cfg_clock_default.h cpu/stm32: fix l4l5wb clock configuration 2020-11-10 09:34:07 +01:00