Alexandre Abadie 934028c114 cpu/stm32: fix l4l5wb clock configuration ... Default values were wrong for WB when using HSE 32MHz as PLL input source Default PLL input source was wrong when not using HSE and the board provides an HSE		2020-11-10 09:34:07 +01:00
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clk	cpu/stm32: fix l4l5wb clock configuration	2020-11-10 09:34:07 +01:00
periph	cpu/stm32: add basic support for stm32l5	2020-10-23 18:21:50 +02:00
vendor	cpu/stm32: configure stm32l5 cmsis repository version	2020-10-23 18:13:07 +02:00
.gitignore	cpu/stm32: add tool to generate a header with IRQ numof defines	2020-09-02 11:30:49 +02:00
can_params.h	boards: enable CAN bus on nucleo-f446re & nucleo-f446ze	2020-07-27 14:36:29 +02:00
candev_stm32.h	cpu/stm32: adapt Doxygen documentation	2020-05-20 13:39:11 +02:00
cpu_conf_stm32_common.h	cpu/stm32: add basic support for stm32l5	2020-10-23 18:21:50 +02:00
cpu_conf.h	cpu/stm32l5: adapt flashpage periph	2020-10-23 18:21:50 +02:00
periph_cpu.h	cpu/stm32: add basic support for stm32l5	2020-10-23 18:21:50 +02:00
stmclk.h	cpu/stm32: adapt Doxygen documentation	2020-05-20 13:39:11 +02:00
usbdev_stm32.h	cpu/stm32: adapt Doxygen documentation	2020-05-20 13:39:11 +02:00