2 Commits

Author	SHA1	Message	Date
Alexandre Abadie	934028c114	cpu/stm32: fix l4l5wb clock configuration ... Default values were wrong for WB when using HSE 32MHz as PLL input source Default PLL input source was wrong when not using HSE and the board provides an HSE	2020-11-10 09:34:07 +01:00
Alexandre Abadie	ec5b47fc61	cpu/stm32l4+/wb: centralize max core clock define, adapt related boards	2020-10-27 08:44:55 +01:00