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https://github.com/RIOT-OS/RIOT.git
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186 lines
4.1 KiB
C
186 lines
4.1 KiB
C
/*
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* Copyright (C) 2017 Ken Rabold
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_fe310
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* @{
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*
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* @file
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Ken Rabold
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*/
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#ifndef PERIPH_CPU_H
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#define PERIPH_CPU_H
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#include <inttypes.h>
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#include "periph_cpu_common.h"
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#include "cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#ifndef DOXYGEN
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/**
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* @brief Overwrite the default gpio_t type definition
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*/
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#define HAVE_GPIO_T
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typedef uint8_t gpio_t;
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#endif
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/**
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* @brief Length of the CPU_ID in octets
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*/
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#define CPUID_LEN (12U)
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/**
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* @brief Definition of a fitting UNDEF value
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*/
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#define GPIO_UNDEF (0xff)
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/**
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* @brief Define a CPU specific GPIO pin generator macro
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*/
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#define GPIO_PIN(x, y) (x | y)
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/**
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* @brief GPIO interrupt priority
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*/
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#define GPIO_INTR_PRIORITY (3)
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/**
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* @brief Structure for UART configuration data
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*/
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typedef struct {
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uint32_t addr; /**< UART control register address */
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gpio_t rx; /**< RX pin */
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gpio_t tx; /**< TX pin */
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irqn_t isr_num; /**< ISR source number */
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} uart_conf_t;
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/**
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* @brief UART interrupt priority
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*/
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#define UART_ISR_PRIO (2)
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/**
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* @name This CPU makes use of the following shared SPI functions
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* @{
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*/
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#define PERIPH_SPI_NEEDS_TRANSFER_BYTE 1
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#define PERIPH_SPI_NEEDS_TRANSFER_REG 1
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#define PERIPH_SPI_NEEDS_TRANSFER_REGS 1
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/** @} */
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/**
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* @brief Structure for SPI configuration data
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*/
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typedef struct {
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uint32_t addr; /**< SPI control register address */
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gpio_t mosi; /**< MOSI pin */
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gpio_t miso; /**< MISO pin */
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gpio_t sclk; /**< SCLK pin */
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} spi_conf_t;
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/**
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* @brief Prevent shared timer functions from being used
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*/
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#define PERIPH_TIMER_PROVIDES_SET
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/**
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* @name Use the shared I2C functions
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* @{
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*/
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/** Use read reg function from periph common */
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#define PERIPH_I2C_NEED_READ_REG
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/** Use write reg function from periph common */
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#define PERIPH_I2C_NEED_WRITE_REG
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/** Use read regs function from periph common */
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#define PERIPH_I2C_NEED_READ_REGS
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/** Use write regs function from periph common */
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#define PERIPH_I2C_NEED_WRITE_REGS
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/** @} */
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#ifndef DOXYGEN
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/**
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* @brief Default mapping of I2C bus speed values
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* @{
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*/
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#define HAVE_I2C_SPEED_T
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typedef enum {
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I2C_SPEED_NORMAL, /**< normal mode: ~100kbit/s */
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I2C_SPEED_FAST, /**< fast mode: ~400kbit/s */
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} i2c_speed_t;
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/** @} */
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#endif /* ndef DOXYGEN */
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/**
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* @brief I2C configuration options
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*/
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typedef struct {
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uint32_t addr; /**< device base address */
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gpio_t scl; /**< SCL pin */
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gpio_t sda; /**< SDA pin */
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i2c_speed_t speed; /**< I2C speed */
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} i2c_conf_t;
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/**
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* @name WDT upper and lower bound times in ms
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* @{
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*/
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#define NWDT_TIME_LOWER_LIMIT (1)
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/* Ensure the internal "count" variable stays within the uint32 bounds.
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This variable corresponds to max_time * RTC_FREQ / MS_PER_SEC. On fe310,
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RTC_FREQ is 32768Hz. The 15 right shift is equivalent to a division by RTC_FREQ.
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*/
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#define NWDT_TIME_UPPER_LIMIT ((UINT32_MAX >> 15) * MS_PER_SEC + 1)
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/** @} */
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/**
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* @brief WDT interrupt priority: use highest priority
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*/
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#define WDT_INTR_PRIORITY (PLIC_NUM_PRIORITIES)
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/**
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* @brief WDT can be stopped
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*/
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#define WDT_HAS_STOP (1)
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/**
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* @name RTT/RTC configuration
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*
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* @{
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*/
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#define RTT_INTR_PRIORITY (2)
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#define RTT_MAX_VALUE (0xffffffff)
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#define RTT_CLOCK_FREQUENCY (32768U) /* in Hz */
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#define RTT_MAX_FREQUENCY (RTT_CLOCK_FREQUENCY) /* in Hz */
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#define RTT_MIN_FREQUENCY (1U) /* in Hz */
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#ifndef RTT_FREQUENCY
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#define RTT_FREQUENCY (RTT_MAX_FREQUENCY) /* in Hz */
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#endif
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/**
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* @brief Initialization of the clock
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*/
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void fe310_clock_init(void);
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CPU_H */
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/** @} */
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