2eb800cb8b
cpu/fe310: use coreclk instead of cpu_freq
2021-12-15 13:14:19 +01:00
Jan Romann
bd7b277f7e
cpu/fe310: uncrustify
2021-11-18 15:44:17 +01:00
Jose Alamos
94d46e756e
cpu/fe310: fix RTT frequency
2021-07-02 14:53:22 +02:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common
2021-02-05 09:32:19 +01:00
ba518ede09
cpu/fe310: Uncrustify code
2021-01-15 12:02:55 +01:00
Benjamin Valentin
2647f5f3c2
cpu/fe310: run RTT at 1 Hz if RTC is selected
...
The RTC on the fe310 is emulated using the RTT.
This only works if the RTT frequency is 1 Hz, so default to that
value in case `periph_rtc` is selected.
2020-09-27 22:45:04 +02:00
Francisco Molina
442b11d0ee
cpu/fe310: add unified rtt configuration
2020-08-12 14:46:59 +02:00
ee3fc27e96
cpu/fe310: implement driver for watchdog
2020-04-07 14:37:55 +02:00
Sören Tempel
bd2f5fe110
fe310: fix power management configuration
2020-01-30 10:43:01 +01:00
Francisco
f76f7c73ce
Merge pull request #12957 from aabadie/pr/cpu/fe310_spi
...
cpu/fe310: add spi peripheral driver
2020-01-14 10:54:47 +01:00
Tristan Bruns
532cdc64ff
cpu/fe310: implement SPI
2020-01-11 13:06:39 +01:00
298d573280
cpu/fe310: provide i2c driver
2020-01-11 13:06:10 +01:00
97e1c7ba7e
cpu/fe310: reorganize files and includes
2020-01-10 16:41:33 +01:00
e5c64c739a
cpu/fe310: rework uart driver implem/config
2019-12-20 15:22:09 +01:00
smlng
740eafe93b
cpu/fe310: add missing PERIPH_TIMER_PROVIDES_SET
2018-09-07 22:15:13 +02:00
kenrabold
7d1d5e77d8
cpu/fe310: add RISC-V cpu FE310
...
New CPU FE310 from SiFive based on RISC-V architecture
build: add makefile for RISC-V builds
Makefile for builds using RISC-V tools
2018-05-29 15:21:45 -07:00
