mirror of
https://github.com/RIOT-OS/RIOT.git
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245 lines
6.4 KiB
C
245 lines
6.4 KiB
C
/*
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* Copyright (C) 2019 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_stm32f723e-disco
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the STM32F723E-DISCO board
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*
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "cfg_rtt_default.h"
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#include "cfg_usb_otg_fs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 216MHz */
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#define CLOCK_CORECLOCK (216000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (25000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 54MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 108MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (25)
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#define CLOCK_PLL_N (432)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (9)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM2,
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.max = 0xffffffff,
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.rcc_mask = RCC_APB1ENR_TIM2EN,
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.bus = APB1,
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.irqn = TIM2_IRQn
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}
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};
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#define TIMER_0_ISR isr_tim2
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART6,
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.rcc_mask = RCC_APB2ENR_USART6EN,
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.rx_pin = GPIO_PIN(PORT_C, 6),
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.tx_pin = GPIO_PIN(PORT_C, 7),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB2,
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.irqn = USART6_IRQn,
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#ifdef MODULE_STM32_PERIPH_UART_HW_FC
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.cts_pin = GPIO_UNDEF,
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.rts_pin = GPIO_UNDEF,
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.cts_af = GPIO_AF8,
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.rts_af = GPIO_AF8,
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#endif
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},
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{ /* Arduino connector (D0/D1) */
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.dev = USART2,
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.rcc_mask = RCC_APB1ENR_USART2EN,
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.rx_pin = GPIO_PIN(PORT_A, 3),
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.tx_pin = GPIO_PIN(PORT_A, 2),
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.rx_af = GPIO_AF7,
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.tx_af = GPIO_AF7,
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.bus = APB1,
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.irqn = USART2_IRQn,
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#ifdef MODULE_STM32_PERIPH_UART_HW_FC
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.cts_pin = GPIO_UNDEF,
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.rts_pin = GPIO_UNDEF,
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.cts_af = GPIO_AF8,
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.rts_af = GPIO_AF8,
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#endif
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},
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{ /* PMOD connector */
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.dev = UART7,
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.rcc_mask = RCC_APB1ENR_UART7EN,
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.rx_pin = GPIO_PIN(PORT_F, 6),
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.tx_pin = GPIO_PIN(PORT_F, 7),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB1,
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.irqn = UART7_IRQn,
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#ifdef MODULE_STM32_PERIPH_UART_HW_FC
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.cts_pin = GPIO_PIN(PORT_F, 9),
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.rts_pin = GPIO_PIN(PORT_F, 8),
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.cts_af = GPIO_AF8,
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.rts_af = GPIO_AF8,
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#endif
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},
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{ /* ESP-01 connector */
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.dev = UART5,
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.rcc_mask = RCC_APB1ENR_UART5EN,
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.rx_pin = GPIO_PIN(PORT_D, 2),
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.tx_pin = GPIO_PIN(PORT_C, 12),
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.rx_af = GPIO_AF8,
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.tx_af = GPIO_AF8,
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.bus = APB1,
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.irqn = UART5_IRQn,
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#ifdef MODULE_STM32_PERIPH_UART_HW_FC
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.cts_pin = GPIO_UNDEF,
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.rts_pin = GPIO_UNDEF,
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.cts_af = GPIO_AF8,
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.rts_af = GPIO_AF8,
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#endif
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},
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};
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#define UART_0_ISR (isr_usart6)
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#define UART_1_ISR (isr_usart2)
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#define UART_2_ISR (isr_uart4)
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#define UART_3_ISR (isr_uart7)
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#define UART_4_ISR (isr_uart5)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name I2C configuration
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* @{
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*/
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static const i2c_conf_t i2c_config[] = {
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{ /* Shared between Arduino D14/D15 and STMOD+ connector */
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.dev = I2C2,
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.speed = I2C_SPEED_NORMAL,
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.scl_pin = GPIO_PIN(PORT_H, 4),
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.sda_pin = GPIO_PIN(PORT_H, 5),
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.scl_af = GPIO_AF4,
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.sda_af = GPIO_AF4,
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.bus = APB1,
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.rcc_mask = RCC_APB1ENR_I2C2EN,
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.irqn = I2C2_ER_IRQn,
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}
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};
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#define I2C_0_ISR isr_i2c2_er
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#define I2C_NUMOF ARRAY_SIZE(i2c_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 54000000Hz */
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7, /* -> 210937Hz */
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6, /* -> 421875Hz */
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5, /* -> 843750Hz */
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3, /* -> 3375000Hz */
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2 /* -> 6750000Hz */
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},
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{ /* for APB2 @ 108000000Hz */
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7, /* -> 421875Hz */
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7, /* -> 421875Hz */
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6, /* -> 843750Hz */
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4, /* -> 3375000Hz */
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3 /* -> 6750000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{ /* Arduino connector */
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_B, 5),
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.miso_pin = GPIO_PIN(PORT_B, 4),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_UNDEF,
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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{ /* PMOD connector */
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.dev = SPI2,
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.mosi_pin = GPIO_PIN(PORT_I, 3),
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.miso_pin = GPIO_PIN(PORT_I, 2),
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.sclk_pin = GPIO_PIN(PORT_I, 1),
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.cs_pin = GPIO_PIN(PORT_I, 0),
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.mosi_af = GPIO_AF5,
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.miso_af = GPIO_AF5,
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.sclk_af = GPIO_AF5,
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.cs_af = GPIO_AF5,
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.rccmask = RCC_APB1ENR_SPI2EN,
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.apbbus = APB1
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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