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RIOT/cpu
bors[bot] 149cee491e
Merge #19760 #19946 #19956 #19957
19760: cpu/sam0_common/periph: add low-level SDMMC peripheral driver for SDHC r=benpicco a=gschorcht

### Contribution description

This PR implements the low-level SDIO/SDMMC peripheral driver for SAM0 SDHC according to the definition in #19539.

### Testing procedure

```
BOARD=same54-xpro make -C tests/drivers/sdmmc
```
```
BOARD=same54-xpro make -C tests/sys/vfs_default
```

### Issues/PRs references

~Depends on PR #19539~
Depends on PR #19899

19946: posix_sockets.c: Fix 2 byte int compilation errors r=benpicco a=mrdeep1



19956: cpu/esp32: fix heap definition for ESP32-S2 and ESP32-S3 r=benpicco a=gschorcht

### Contribution description

For ESP32-S2 and ESP32-S3 the symbol `_heap_end` must not be used as `_eheap` for the newlibc `malloc` and function `sbrk`.

`_heap_end` is used by the ESP-IDF heap implementation `esp-idf-heap` and points to the highest possible address (0x40000000) that could be used for the heap in ESP-IDF. It doesn't point to the top address of the unused SRAM area that can be used in newlibc `malloc` and function `sbrk`. Instead, the origin and the length of `dram0_0_seg` must be used to calculate the end of the heap `_eheap`.

The problem only occurs for the newlibc `malloc` when the `sbrk` function is used but not for the ESP-IDF heap implementation `esp_idf_heap`.

### Testing procedure

Use any ESP32-S2 or ESP32-S3 board and flash `tests/sys/malloc`, e.g.
```
CFLAGS='-DCHUNK_SIZE=16384' USEMODULE='stdio_uart' BOARD=esp32s3-pros3 make -j8 -C tests/sys/malloc flash
```
Without the PR the `nm` command will give the wrong address 
```
nm -s tests/sys/malloc/bin/esp32s3-pros3/tests_malloc.elf | grep _eheap
40000000 A _eheap
```
The test will stuck, i.e. the allocation of memory stops when the top of unused SRAM is reached and the board restarts when the watchdog timer expires. With the PR it should work as expected
```
Help: Press s to start test, r to print it is ready
START
main(): This is RIOT! (Version: 2023.10-devel-309-g4669e)
calloc(zu, zu) = 0x10000000
CHUNK_SIZE: 16384
NUMBER_OF_TESTS: 3
Allocated 16384 Bytes at 0x3fc8c4b0, total 16384
...
Allocated 16384 Bytes at 0x3fcec6f0, total 409792
ESP-ROM:esp32s3-20210327
Build:Mar 27 2021
rst:0x7 (TG0WDT_SYS_RST),boot:0x8 (SPI_FAST_FLASH_BOOT)
Saved PC:0x403763e3
```

With this PR the `nm` command should give a address in unused SRAM address space
```
nm -s tests/sys/malloc/bin/esp32s3-pros3/tests_malloc.elf | grep _eheap
3fcca000 A _eheap
```
and the test should pass.

### Issues/PRs references


19957: cpu/esp32: fix Octal SPI RAM for ESP32-S3 r=benpicco a=gschorcht

### Contribution description

This PR fixes Octal SPI RAM handling for ESP32-S3.

Functions that are used during the initialization of the Octal SPI RAM must reside in IRAM instead of Flash. Otherwise, the system stucks during boot once the Octal SPI RAM is enabled. The reason is that the Flash is not available during the initialization of the Octal SPI RAM and the functions that are called during that initialization can't be accessed in Flash. As a result the call of such a function leads to code that is messed up and the system crashes.

The PR also includes the documentation fixe for the `esp32s3-box`. It also includes a small documentation fix regarding the SPI RAM for the `esp32s3-pros3` board.

### Testing procedure

Use a board that has Octal SPI RAM and flash `tests/sys/malloc`, e.g.:
```
CFLAGS='-DCHUNK_SIZE=16384' USEMODULE='stdio_uart esp_spi_ram esp_log_startup' \
BOARD=esp32s3-box make -C tests/sys/malloc
```
Without the PR, the system stuck during boot once the information for the Octal SPI RAM is print
```
ESP-ROM:esp32s3-20210327
...
I (133) boot: Loaded app from partition at offset 0x10000
I (134) boot: Disabling RNG early entropy source...
vendor id : 0x0d (AP)
dev id    : 0x02 (generation 3)
density   : 0x03 (64 Mbit)
good-die  : 0x01 (Pass)
Latency   : 0x01 (Fixed)
VCC       : 0x01 (3V)
SRF       : 0x01 (Fast Refresh)
BurstType : 0x01 (Hybrid Wrap)
BurstLen  : 0x01 (32 Byte)
Readlatency  : 0x02 (10 cycles@Fixed)
DriveStrength: 0x00 (1/1)
```
and the board restarts when the watchdog timer expires.

With this PR, the system starts as expected.
```
ESP-ROM:esp32s3-20210327
...
I (132) boot: Loaded app from partition at offset 0x10000
I (133) boot: Disabling RNG early entropy source...
vendor id : 0x0d (AP)
dev id    : 0x02 (generation 3)
density   : 0x03 (64 Mbit)
good-die  : 0x01 (Pass)
Latency   : 0x01 (Fixed)
VCC       : 0x01 (3V)
SRF       : 0x01 (Fast Refresh)
BurstType : 0x01 (Hybrid Wrap)
BurstLen  : 0x01 (32 Byte)
Readlatency  : 0x02 (10 cycles@Fixed)
DriveStrength: 0x00 (1/1)
Found 64MBit SPI RAM device
SPI RAM mode: sram 40m
PSRAM initialized, cache is in normal (1-core) mode.
Pro cpu up.
Single core mode
SPI SRAM memory test OK
Initializing. RAM available for dynamic allocation:
At 3FC8C150 len 00053EB0 (335 KiB): D/IRAM
At 3FCE0000 len 0000EE34 (59 KiB): STACK/DRAM
At 3FCF0000 len 00008000 (32 KiB): DRAM

Starting ESP32x with ID: f412fafd0f8c
ESP-IDF SDK Version v4.4.1

Current clocks in Hz: CPU=80000000 APB=80000000 XTAL=40000000 SLOW=150000
PRO cpu is up (single core mode, only PRO cpu is used)
PRO cpu starts user code
Adding pool of 8192K of external SPI memory to heap allocator
Used clocks in Hz: CPU=80000000 APB=80000000 XTAL=40000000 FAST=8000000 SLOW=150000
XTAL calibration value: 3643448
Heap free: 8754851 bytes

Board configuration:
	UART_DEV(0)	txd=43 rxd=44
	LED		pins=[ ]
	BUTTONS		pins=[ 0 ]

Starting RIOT kernel on PRO cpu
Help: Press s to start test, r to print it is ready
```

### Issues/PRs references


Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Jon Shallow <supjps-libcoap@jpshallow.com>
2023-09-29 08:36:50 +00:00
..
arm7_common cpu/arm7: Fix undefined behavior based on invalid assembly 2023-05-19 11:34:30 +02:00
atmega8 cpu/atmega_common: some additional periph drivers fixed for atmega8 cpu 2023-07-11 21:22:02 +02:00
atmega32u4 cpu/atmega_common: implement periph/gpio_ll{,_irq} 2022-05-02 14:44:55 +02:00
atmega128rfa1 cpu/atmega128rfa1/Kconfig: select default transceiver 2023-01-19 15:34:19 +01:00
atmega256rfr2 cpu/atmega256rfr2/Kconfig: select default transceiver 2023-01-19 15:34:19 +01:00
atmega328p cpu/atmega_common: implement periph/gpio_ll{,_irq} 2022-05-02 14:44:55 +02:00
atmega1281 cpu/atmega_common: implement periph/gpio_ll{,_irq} 2022-05-02 14:44:55 +02:00
atmega1284p cpu/atmega_common: implement periph/gpio_ll{,_irq} 2022-05-02 14:44:55 +02:00
atmega2560 cpu/atmega_common: implement periph/gpio_ll{,_irq} 2022-05-02 14:44:55 +02:00
atmega_common cpu/atmega_common: hook up BAT LOW irq to power bus 2023-07-12 14:52:05 +02:00
atxmega cpu/avr8_common: Add AVR8_ISR macro 2023-07-05 20:00:19 +02:00
avr8_common cpu/avr8_common: Add AVR8_ISR macro 2023-07-05 20:00:19 +02:00
cc26x0_cc13x0 cpu/cc26x0_cc13x0: Drop feature cortexm_mpu 2023-04-26 10:51:52 +02:00
cc26x2_cc13x2 cpu: call early_init() 2023-01-08 22:26:12 +01:00
cc26xx_cc13xx cpu/cc26xx_cc13xx: Fix bogus array-bound warning 2023-04-25 15:31:27 +02:00
cc2538 cpu: call early_init() 2023-01-08 22:26:12 +01:00
cortexm_common core/thread: drop unused thread_arch_t 2023-05-21 22:17:52 +02:00
efm32 cpu/efm32: add EFM32GG11 family 2023-09-18 12:40:33 +02:00
esp32 Merge #19760 #19946 #19956 #19957 2023-09-29 08:36:50 +00:00
esp8266 cpu/esp8266: fix region overflow with '*periph' directory in app path 2023-07-02 12:21:16 +02:00
esp_common cpu/esp_common: esp-wifi: drop assert(val) 2023-08-01 23:06:11 +02:00
fe310 cpu/riscv: Add PMP driver 2023-06-28 11:55:34 +02:00
gd32v tree wide: fix typos in comments found by codespell 2023-05-02 09:52:06 +02:00
kinetis cpu: call early_init() 2023-01-08 22:26:12 +01:00
lm4f120 cpu: call early_init() 2023-01-08 22:26:12 +01:00
lpc23xx cpu: Add TLS symbols for newer picolibc to linker scripts 2023-03-02 22:55:22 -08:00
lpc1768 cpu: call early_init() 2023-01-08 22:26:12 +01:00
msp430 cpu/msp430: make use of vendor header files 2023-07-04 20:21:05 +02:00
native drivers/periph/rtc: improve doc on rtc_set_alarm 2023-05-30 17:41:36 +02:00
nrf5x_common Merge #19634 2023-07-18 10:47:46 +00:00
nrf51 cpu/nrfxx: simplify LFCLK source selection 2023-07-06 15:47:22 +02:00
nrf52 pkg: Add cryptocell driver and nrf52 HW features 2023-08-31 14:38:49 +02:00
nrf53 boards/nrf5340dk-app: add SPI flash configuration and I2C pins 2023-07-12 21:51:50 +02:00
nrf9160 cpu/nrfxx: use shared serial IRQ 2023-07-11 22:42:10 +02:00
qn908x cpu/qn908x/periph_i2c: enable internal pull-up on SCL 2023-06-13 14:43:36 +02:00
riscv_common cpu/riscv_common: remove picolibc from blacklisting in CI 2023-08-07 13:21:40 +02:00
rpx0xx cpu/rpx0xx: Fix kconfig model 2023-05-24 09:53:23 +02:00
sam0_common cpu/sam0_common: add SDMMC support 2023-09-23 19:26:30 +02:00
sam3 cpu/sam3: assert valid freq in timer_init() 2023-09-15 12:58:31 +02:00
sam_common cpu/sam_common: make use of cortexm.ld 2022-09-23 15:55:12 +02:00
samd5x cpu/samd5x: define power modes 2023-09-23 19:26:30 +02:00
samd21 cpu/sam0_common: move adc_res_t to common code 2023-01-17 17:18:07 +01:00
saml1x cpu/sam0_common: move adc_res_t to common code 2023-01-17 17:18:07 +01:00
saml21 treewide: fix path to ztimer test applications 2023-05-13 19:08:38 +02:00
stellaris_common cpu: do not locally export compilation variables 2019-08-29 10:35:53 +02:00
stm32 Merge #19952 2023-09-28 10:41:28 +00:00
doc.txt docs/doxygen : Add CPU section 2021-07-09 10:47:42 +02:00
Kconfig treewide: change Kconfig prefix for module symbols 2020-08-31 09:57:28 +02:00