1
0
mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Commit Graph

3823 Commits

Author SHA1 Message Date
Kees Bakker
2d04cdfb89 cpu/native: do normal assignment instead of memcpy 2019-01-10 19:43:43 +01:00
Kees Bakker
0935bd53d2 cpu/cc430: do normal assignment instead of memcpy 2019-01-10 19:43:43 +01:00
Kevin "Bear Puncher" Weiss
0b23e8898e
Merge pull request #10641 from gschorcht/esp32_spi_revision
cpu/esp32: cleanup in periph/spi
2019-01-09 14:02:06 +01:00
Gunar Schorcht
6b045f14b7 cpu/esp32: cleanup of SPI interfaces in doc
Although ESP32 has four SPI controllers, only two of them can be effectively used (HSP and VSPI). The third one (FSPI) is used for external memory such as flash and PSRAM and can not be used for peripherals. FSPI is therefore removed from the API. In addition, the SPI0_DEV and SPI1_DEV configuration parameters are renamed SPI0_CTRL and SPI1_CTRL to better describe what they define and to avoid confusion with SPI_DEV (0) and SPI_DEV (1).
2019-01-09 13:03:56 +01:00
Gunar Schorcht
437f8b87b9 cpu/esp32: cleanup of SPI interfaces
Although ESP32 has four SPI controllers, only two of them can be effectively used (HSP and VSPI). The third one (FSPI) is used for external memory such as flash and PSRAM and can not be used for peripherals. FSPI is therefore removed from the API. In addition, the SPI0_DEV and SPI1_DEV configuration parameters are renamed SPI0_CTRL and SPI1_CTRL to better describe what they define and to avoid confusion with SPI_DEV (0) and SPI_DEV (1).
2019-01-09 13:03:22 +01:00
86c102e85b cpu/stm32_common: move dma attribute at end of config 2019-01-08 09:32:18 +01:00
8a9d9e70bc cpu/stm32f2: update CMSIS of stm32f207xx 2019-01-08 09:32:18 +01:00
Vincent Dupont
8c99edc18e cpu/stm32_common: fix UART ISR_TXE usage 2019-01-08 09:32:18 +01:00
Vincent Dupont
021697ae94 cpu/stm32_common: adapt DMA driver for f0/1/3/l0/1/4 2019-01-08 09:32:18 +01:00
Bas Stottelaar
28d0e46882 cpu: efm32: add support for 32-bit timers 2019-01-07 18:49:21 +01:00
ZetaR60
859ba1a71f
Merge pull request #10699 from MrKevinWeiss/pr/fixbaudmega2560
cpu/atmega_common/uart: Comment why brr calc is different from datasheet
2019-01-07 10:21:15 -05:00
MrKevinWeiss
3ce03df0ff cpu/atmega_common/uart: Comment why brr calc is different from datasheet
The brr calculation on the datasheet is different than what is implmented.
This is intentional since it provides better rounding due to truncation.
There was no comment explaining that so this comment should prevent confusion.
2019-01-07 08:40:21 +01:00
Gunar Schorcht
f7e524d18e
Merge pull request #10604 from gschorcht/esp32_esp_eth_fix
cpu/esp32: Fixes the maximum packet size of 255 bytes in the esp_eth netdev driver of ESP32 mcu.
2019-01-04 12:48:11 +01:00
Gunar Schorcht
dc2b1deff5 cpu/esp32: restructures _recv function in esp_eth 2019-01-04 12:12:28 +01:00
Gunar Schorcht
8318779bc2 cpu/esp32: replaces LOG_ERROR by DEBUG in esp_eth 2019-01-04 12:12:28 +01:00
Gunar Schorcht
1e3abebd86 cpu/esp32: fixes esp_net maximum packet size
Fixes the maximum packet size of 255 bytes in the esp_eth netdev driver of ESP32 mcu.

fixup! cpu/esp32: fixes esp_net maximum packet size
2019-01-04 12:12:13 +01:00
Kevin "Bear Puncher" Weiss
9554f751d8
Merge pull request #6630 from OTAkeys/pr/cortex-m4f-fpu
cortexm_common: add FPU support for cortex-m4f and cortex-m7
2019-01-04 11:56:18 +01:00
b6b1a6bd63
Merge pull request #10683 from basilfx/feature/efm32_gecko_sdk_update
pkg: gecko_sdk: bump version + vendor headers
2019-01-04 10:40:44 +01:00
Vincent Dupont
06f0c14460 cortexm_common: enable FPU on cortex-m4f 2019-01-03 15:24:20 +01:00
Kevin "Bear Puncher" Weiss
d9f26dbbe2
Merge pull request #10636 from aabadie/pr/cpu/nrf5x_gpio_common
cpu/nrf5x: move periph_gpio/periph_gpio_irq at an even more common level
2019-01-03 11:37:48 +01:00
Kevin "Bear Puncher" Weiss
2bf29dd99e
Merge pull request #10692 from aabadie/pr/boards/nucleo-f767_i2c
boards/nucleo-f767zi: use common STM32 i2c configuration
2019-01-03 10:17:44 +01:00
f6985c5b31 cpu/stm32f0: update stm32f072xb CMSIS header 2019-01-02 16:08:56 +01:00
9a61febf5c cpu/stm32f7: update stm32f767zi cmsis header file 2019-01-02 16:06:34 +01:00
Bas Stottelaar
7372074223 cpu: efm32: update vendor headers 2018-12-30 23:35:57 +01:00
Timo Rothenpieler
6be81fbd93 esp_now: use custom netif instead of raw one
Avoids parsing IPv6 packets to determine destination address.
Allows using 6Lo over ESP-NOW, which is required due to the low MTU of
ESP-NOW.

Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
2018-12-29 13:15:44 +01:00
Timo Rothenpieler
34c42cbcc2 esp_now: code style amendments 2018-12-28 13:35:46 +01:00
Timo Rothenpieler
a46023a523 esp_now: remove unnecessary ifdef 2018-12-28 13:35:46 +01:00
Martine Lenders
9f0dfb5222 esp_now: fix doxygen groups 2018-12-28 12:14:16 +01:00
Martine Lenders
380d19e9d2
Merge pull request #10660 from aabadie/pr/periph/stm32_lpuart_l496zg
boards/nucleo-l496zg: use lpuart1 as stdio interface
2018-12-27 19:32:17 +01:00
Gunar Schorcht
797a894e40 cpu/esp32: esp_now netdev moved to esp_common 2018-12-27 17:31:34 +01:00
Gunar Schorcht
a352500476 cpu/esp_common: added for common files for ESP SoC 2018-12-27 17:28:46 +01:00
b2c3df3381 cpu/stm32/gpio: power up port G with L4
Co-authored-by: Vincent Dupont <vincent@otakeys.com>
2018-12-27 14:15:25 +01:00
8449324cf8
Merge pull request #10610 from MrKevinWeiss/pr/fix/stmi2c1
cpu/stm_common: Refactor and cleanup i2c_1
2018-12-21 14:55:35 +01:00
Dylan Laduranty
764c7d2cc1
Merge pull request #10069 from fedepell/sam0_flashwrite
sam0 flashpage_write: correct translation from RIOT pages to CPU pages writing
2018-12-21 14:17:20 +01:00
Federico Pellegrin
b8b8ffd163 sam0 flashpage_write: correct assert for last byte of flash + style 2018-12-21 13:11:38 +01:00
Vincent Dupont
5e67986775 cpu/stm32_common/pm: use CPU_LINE for L053-specific code 2018-12-21 11:24:43 +01:00
Vincent Dupont
4aadc1ed39 cpu/stm32l0: make use of CPU_LINE_ 2018-12-21 11:24:43 +01:00
Vincent Dupont
f28e7a9b01 cpu/stm32l0: use STM32_FLASHSIZE to generate FLASHPAGE_NUMOF 2018-12-21 11:18:43 +01:00
Vincent Dupont
1cea9871e0 cpu/stm32f1: remove ErrorStatus enum from vendor header
This enum conflicts with macro definitions from ccn-lite pkg.
2018-12-21 09:17:30 +01:00
Vincent Dupont
8cdc219e50 cpu/stm32f1: make use of CPU_LINE_ 2018-12-21 09:17:30 +01:00
Vincent Dupont
d133baca2c cpu/stm32f1: use STM32_FLASHSIZE to generate FLASHPAGE_NUMOF 2018-12-21 09:17:30 +01:00
MrKevinWeiss
f3b2a62c67 cpu/stm_common: Refactor and cleanup i2c_1
Refactor to use common read_regs.
Add error reporting and handling for unsupported low level commands.
Document hardware constraints.
2018-12-20 18:05:11 +01:00
ab061c4ae2
Merge pull request #10608 from MrKevinWeiss/pr/fix/stmi2c2
cpu/stm_common: Refactor and fix implementation for i2c_2
2018-12-20 13:51:39 +01:00
MrKevinWeiss
a2e059d18a cpu/stm_common: Refactor and fix implementation for i2c_2
Refactors i2c_2 to match the structure of i2c_1 better.
Corrects functionality issues.
Allows the common implementation of read_regs and write_regs.
Documents constraints of hardware.
Matches error messages with API.
2018-12-20 12:01:06 +01:00
Sebastian Meiling
c96021b039
Merge pull request #10637 from aabadie/pr/cpu/stm32_periph_gpio_common
boards*: move periph_gpio and periph_gpio_irq features from boards to cpu for STM32
2018-12-19 13:06:17 +01:00
Leandro Lanzieri
b32da1b13e
Merge pull request #10615 from MrKevinWeiss/pr/debug/init
cpu/stm32_common/uart: Prevent uart from sending if not initialized
2018-12-19 12:14:00 +01:00
Federico Pellegrin
a0054654ee sam0 flashpage_write: fix writes translation from RIOT to CPU pages 2018-12-19 04:54:44 +01:00
da3bb42d18 cpu/stm32_common: define periph_gpio/irq features at cpu level 2018-12-18 21:50:34 +01:00
220d16dc07 cpu/nrf5x: move periph_gpio features to common cpu level 2018-12-18 21:32:46 +01:00
7a6849ca17 cpu/cortexm_common: add riotboot and slot support
RIOTBOOT_SLOT_LEN is calculated as an hexadecimal value and
handles ROM_LEN defined as kilobytes like '512K'

This enables support for all the cortex-m0+/3/4/7 arch,
so most boards embedding these are potentially supported.
One needs just to ensure that the CPU can be initialised
at least twice.

Co-authored-by: Gaëtan Harter <gaetan.harter@fu-berlin.de>
2018-12-18 19:31:35 +01:00