Benjamin Valentin
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ea917f4b07
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cpu: cpu_print_last_instruction() -> cpu_get_caller_pc()
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2022-09-15 10:49:56 +02:00 |
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PeterKietzmann
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6215b7e630
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cpu/riscv_common: add puf_sram feature
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2022-02-16 15:18:37 +01:00 |
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Benjamin Valentin
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41a5b7ef7a
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core: change return type of irq_is_in(), irq_is_enabled() to bool
This only cleans up the API, no change in behavior or users of the API
is expected.
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2021-12-08 15:53:15 +01:00 |
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Jan Romann
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3056b89252
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cpu/riscv_common: uncrustify
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2021-11-19 00:20:12 +01:00 |
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Benjamin Valentin
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3e20e939c6
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cpu: drop cpu_init() from public headers
Boards are no longer supposed fo call the function, so drop it from
public header files.
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2021-10-18 17:31:26 +02:00 |
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Jean-Pierre De Jesus DIAZ
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22a7e1af03
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cpu/riscv_common: fix doxygen grouping warnings
Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
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2021-09-11 12:45:15 +02:00 |
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Hauke Petersen
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9a5edcf839
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cpu/riscv: implement irq_is_enabled()
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2021-08-25 08:01:05 +02:00 |
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benpicco
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025770968b
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Merge pull request #16036 from bergzand/pr/gd32vf103/initial
gd32v/seeedstudio-gd32: Initial support
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2021-08-25 00:38:00 +02:00 |
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f2787448e1
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cpu/riscv_common: Move MCAUSE defines to riscv_common
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2021-08-24 14:30:23 +02:00 |
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48aa533639
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cpu/riscv_common: Add CLIC peripheral driver
The CLIC is a next generation interrupt controller for the RISC-V
architecture.
Co-authored-by:
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2021-08-24 10:30:18 +02:00 |
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9239c2fe14
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cpu/riscv_common: Add bit set and clear functions
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2021-08-24 10:30:15 +02:00 |
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Jan Romann
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4384795cb9
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treewide: Remove excessive newlines
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2021-08-13 19:50:38 +02:00 |
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0b2810a856
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riscv_common: make thread_yield_higher IRQ compatible
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2021-02-08 11:04:18 +01:00 |
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2692957c0e
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riscv_common: Refactor common fe310 code to riscv_common
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2021-02-05 09:32:19 +01:00 |
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