The `i2c_read_bytes()` and `i2c_write_bytes()` function return the
number of bytes written / read, instead of `0` as the API contract
says. This fixes the issue.
With only 8 possible prescalers, we can just loop over the values
and shift the clock. In addition to being much easier to read, using
shifts over divisions can be a lot faster on CPUs without hardware
division.
In addition an `assert()` is added that checks if the API contract
regarding the SPI frequency is honored. If the requested clock is too
low to be generated, we should rather have a blown assertion than
hard to trace communication errors.
Finally, the term prescaler is used instead of divider, as divider may
imply that the frequency is divided by the given value n, but
in fact is divided by 2^(n+1).
Previously, the /CS signal was performed by enabling / disabling the
SPI peripheral. This had the disadvantage that clock polarity settings
where not applied starting with `spi_acquire()`, as assumed by e.g.
the SPI SD card driver, but only just before transmitting data.
Now the SPI peripheral is enabled on `spi_acquire()` and only disabled
when calling `spi_release()`, and the `SPI_CR2_SSOE` bit in the `CR2`
register is used for hardware /CS handling (as supposed to).
This doesn't change the firmware, since for all STM32 MCUs with an
SPI driver the register setting in the mode did match the SPI mode
number by chance. But for some STM32 MCUs with no SPI driver yet
the register layout is indeed different. This will help to provide an
SPI driver for them as well.
This makes it easier to use common error reporting such as `strerror()`
or `tiny_strerror()` to give more insight on why something failed.
The custom error codes via `enum` have been updated to be synonymous
with the `errno` codes for backward compatibility.
In addition, `pcf857x_init()` has been updated to no longer or
together the return code, but rather abort on the first fail transaction
and return the error code as is. Otherwise (when both fail due to
different error codes) the returned error code may be garbage.
The CR2 register was only written to if the settings differ from the
reset value. This wasn't actually a bug, since it was cleared in
`spi_release()` to the reset value again. Still, it looks like a bug,
may cause a pipeline flush due to the branch, and increased `.text`
size. So let's get rid of this.
The `SWJ_CFG` field of the `AFIO_MAPR` register is write only and values
read are undefined (random). Hence, using `AFIO->MAPR |= mask;` to
enable flags can corrupt the state of the `SWJ_CFG` (configure it to
an unintended value).
Two helper functions have been introduced:
- `afio_mapr_read()` reads the value, but sanitizes the `SWJ_CFG` field
to zero
- `afio_mapr_write()` writes the given value, but applies the `SWJ_CFG`
configured by the board before writing.
Finally, the `nucleo-f103rb` and `bluepill*`/`blackpill*` boards have
been updated to no longer specify `STM32F1_DISABLE_JTAG`, as this
is handled by the `SWJ_CFG` setting (which defaults to disabling JTAG).
- Detect when the same timer is used by `ztimer` (pulled in as
dependency for a peripheral driver, e.g. `periph_adc` on STM32F3) and
the test application
- Try to provide a better default (e.g. `TIMER_DEV(1)` when
`ztimer_periph_timer` is in use, `TIMER_DEV(0)` otherwise)
The R-2R resistor ladder dac --> ADC test was disabled due to a bug in
the v0.1 version of the shield. Since this has been fixed in v0.2 and
v0.3 of the shield, it can be re-enabled.
The comment regarding the high accuracy of the resistor is dropped, as
v0.3 has been ordered with cost efficient resistors rather than with
accurate ones. As a result, the tolerance for error has been increased
to 10%. This quite a bit more lax than I have hoped for, but false
positives would be something to avoid.
- fix a copy-paste error (`TIMER_FREQ_UART_TEST` was used in the SPI
test, but that should be `TIMER_FREQ_SPI_TEST`)
- use 400 kHz as slow SPI frequency, as faster STM32 MCUs just cannot
divide the APB clock down to 100 kHz
- when detailed output is enabled, print the SPI clock in addition to
the SPI mode to ease figuring out what went wrong
- only have one `FAILURE` message for a too fast byte transfer per
check, rather than per transmitted byte, to reduce the noise
- work around a bug of `periph_timer` on STM32 by reducing the clock
speed of the timer for the SPI test
