4 Commits

Author	SHA1	Message	Date
Leandro Lanzieri	cf753c6790	cpu/riscv_common: model Kconfig	2021-10-01 11:26:15 +02:00
Karl Fessel	fe03c4c059	cpu/riscv,gd32: match Kconfig to Makefile changes	2021-09-22 15:50:28 +02:00
Benjamin Valentin	a9c83017ee	cpu/riscv_common: only select PLIC for fe310 ... Not every RISC-V implements that interrupt controller, gd32v uses CLIC instead.	2021-08-25 10:49:47 +02:00
Koen Zandberg	2692957c0e	riscv_common: Refactor common fe310 code to riscv_common	2021-02-05 09:32:19 +01:00