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Commit Graph

75 Commits

Author SHA1 Message Date
Gilles DOFFE
e4fa203db4 cpu/stm32: STM32MP1 family has no flash
Then CPU_FLASH_BASE cannot be defined as FLASH_BASE does not exist.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
2ac0467807 cpu/stm32: configure timer2 for stm32mp1 boards
This timer will be used by RIOT-OS as the scheduling timer for
stm32mp157c-dk2 board.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
504fba61b8 cpu/stm32: add uart support for stm32mp1
stm32mp1 family uart driver is the same than for other stm32 families.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
be2c0ae179 cpu/stm32: define CPU_IRQ_NUMOF for stm32mp157cac
This MCU has 150 interrupt vectors.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
d6400c77de cpu/stm32: include stm32mp1 vendor headers
Include stm32mp1 vendors header. CORE_CM4 must be defined to include
Cortex-M4 core headers.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
169097ac21 cpu/stm32: add stm32mp157x vendor headers
Add vendor CMSIS headers from STMicroelectronics:
https://wiki.st.com/stm32mpu/wiki/STM32CubeMP1_architecture#CMSIS

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
4f0fd9cf95 cpu/stm32: add GPIO_PIN macro for stm32mp1 family
As stm32mp1 family accesses gpio pins with a different
offset than other stm32, create a specific macro.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
7a2550da9b cpu/stm32: add stm32mp1 peripheral busses
Add stm32mp1 peripheral busses AHB1, AHB2, AHB3 and AHB4 with
enable/disable functions.

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
67f37950a0 cpu/stm32: default i2c configuration
* Setup i2c speed to I2C_SPEED_LOW by default
* enable i2c_write_regs() function.
* i2c frequency needs to be specified into board periph_conf.h

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
Gilles DOFFE
f39aa979af cpu/stm32: setup CLOCK_LSI for stm32mp1
Set stm32mp1 family LSI clock frequency to 32KHz as specified in datasheet.
STM32MP157C example:
https://www.st.com/resource/en/datasheet/stm32mp157c.pdf

Signed-off-by: Gilles DOFFE <gilles.doffe@savoirfairelinux.com>
2020-11-13 10:43:08 +01:00
1c063a74ea
stm32: Adapt to flashpage/flashpage_pagewise API 2020-11-11 23:16:42 +01:00
2f2622c76f
cpu/stm32: move stm32l5 default PLL N to cpu 2020-11-10 09:34:07 +01:00
36d33d38f7
cpu/stm32: move stm32l4+ default PLL N to cpu 2020-11-10 09:34:07 +01:00
934028c114
cpu/stm32: fix l4l5wb clock configuration
Default values were wrong for WB when using HSE 32MHz as PLL input source
Default PLL input source was wrong when not using HSE and the board
provides an HSE
2020-11-10 09:34:07 +01:00
ec5b47fc61
cpu/stm32l4+/wb: centralize max core clock define, adapt related boards 2020-10-27 08:44:55 +01:00
05f67a0a00
cpu/stm32: remove useless include in clock configuration 2020-10-26 11:21:07 +01:00
d6d85a3370
cpu/stm32: add common clock configuration header 2020-10-26 11:21:07 +01:00
f2e2c89424
cpu/stm32: move clock configuration headers to cpu 2020-10-26 11:16:23 +01:00
7f26d5c389
cpu/stm32l5: adapt flashpage periph 2020-10-23 18:21:50 +02:00
a416b2793f
cpu/stm32: add basic support for stm32l5 2020-10-23 18:21:50 +02:00
02c4b05a5a
cpu/stm32: configure stm32l5 cmsis repository version 2020-10-23 18:13:07 +02:00
2e2b87dda5
cpu/stm32: define EEPROM size for stm32l011k4 2020-10-15 16:24:33 +02:00
Marian Buschsieweke
6294382627
cpu/stm32: Use mii.h for periph_eth
Use shared MII definitions and utilities instead own definitions.
2020-10-12 08:46:20 +02:00
Marian Buschsieweke
7920d32e32
cpu/stm32: Clean up periph_eth
Use `addr` instead of `mac` when referring to L2 address.
2020-10-05 16:03:47 +02:00
ec2e1a15f9
cpu/stm32: move cmsis package Makefile to stm32 cpu 2020-09-02 11:30:49 +02:00
91c9b8c1b0
cpu/stm32: remove hardcoded CPU_IRQ_NUMOF defines 2020-09-02 11:30:49 +02:00
39d95b1950
cpu/stm32: add tool to generate a header with IRQ numof defines 2020-09-02 11:30:49 +02:00
hugues
6959a905a2 cpu/stm32/include/periph/f3/periph_cpu.h: add ADC support 2020-08-27 15:43:43 +02:00
5fab8f7a9a
stm32: Add define for when DMA channel selection is not supported
This adds a placeholder define for when the DMA peripheral available on
the MCU doesn't support channel/trigger filtering. This is the case on
the stm32f1 and stm32f3 family.
2020-08-19 16:09:55 +02:00
b9d62e47d3
stm32: Add support for arbitrary SPI clock rates 2020-08-18 16:55:01 +02:00
benpicco
22d3bf7c51
Merge pull request #14594 from maribu/stm32-eth-cleanup
cpu/stm32: Clean up / fix periph_eth
2020-08-17 21:16:27 +02:00
Marian Buschsieweke
4fcf37c162
cpu/stm32/periph_eth: Handle lost & spurious IRQs
Fixes https://github.com/RIOT-OS/RIOT/issues/13496
2020-08-17 20:30:16 +02:00
Marian Buschsieweke
8d8af31e39
driver/stm32_eth: Integrate into periph_eth
The stm32_eth driver was build on top of the internal API periph_eth, which
was unused anywhere. (Additionally, with two obscure exceptions, no functions
where declared in headers, making them pretty hard to use anyway.)

The separation of the driver into two layers incurs overhead, but does not
result in cleaner structure or reuse of code. Thus, this artificial separation
was dropped.
2020-08-17 20:29:33 +02:00
Marian Buschsieweke
932c311ee2
cpu/stm32/periph_eth: Fix RX logic
If any incoming frame is bigger than a single DMA buffer, the Ethernet DMA will
split the content and use multiple DMA buffers instead. But only the DMA
descriptor of the last Ethernet frame segment will contain the frame length.

Previously, the frame length calculation, reassembly of the frame, and the
freeing of DMA descriptors was completely broken and only worked in case the
received frame was small enough to fit into one DMA buffer. This is now fixed,
so that smaller DMA buffers can safely be used now.

Additionally the interface was simplified: Previously two receive flavors were
implemented, with only one ever being used. None of those function was
public due to missing declarations in headers. The unused interface was
dropped and the remaining was streamlined to better fit the use case.
2020-08-17 20:28:49 +02:00
Marian Buschsieweke
234a720571
Merge pull request #14516 from benpicco/bitband_hw
cortexm_common: fix check for bitbanding feature
2020-08-08 14:26:49 +02:00
millotp
69858916c7 boards: enable CAN bus on nucleo-f446re & nucleo-f446ze
Changed the pinout for the CAN bus:
CAN RX: PB8
CAN TX: PB9

And added periph_can to FEATURES_PROVIDED and to Kconfig files
2020-07-27 14:36:29 +02:00
Marian Buschsieweke
a5dbec33d9
cpu/stm32/periph_eth: Cleanup & fix DMA descriptor
- Add missing `volatile` to DMA descriptor, as memory is also accessed by the
  DMA without knowledge of the compiler
- Dropped `__attribute__((packed))` from DMA descriptor
    - The DMA descriptor fields need to be aligned on word boundries to
      properly function
    - The compiler can now more efficiently access the fields (safes ~300 B ROM)
- Moved the DMA descriptor struct and the flags to `periph_cpu.h`
    - This allows Doxygen documentation being build for it
    - Those types and fields are needed for a future PTP implementation
- Renamed DMA descriptor flags
    - They now reflect to which field in the DMA descriptor they refer to, so
      that confusion is avoided
- Added documentation to the DMA descriptor and the corresponding flags
2020-07-26 22:12:03 +02:00
Gunar Schorcht
044d08d599 cpu/stm32: GPIO ports definition fix
The available GPIO ports may also differ within a family. Therefore, the vendor definitions GPIO* are used instad of CPU_FAM_STM definitions to determine which ports are available for a certain MCU.
2020-07-22 09:13:52 +02:00
dada52ecd2
cpu/stm32: add stm32g0 support 2020-07-21 12:45:25 +02:00
8e87dedbce
cpu/stm32: remove not needed CMSIS vendor headers 2020-07-16 17:35:49 +02:00
f21440b176
cpu/stm32: use CMSIS headers from the stm32cmsis package 2020-07-16 17:35:48 +02:00
Benjamin Valentin
8f36c88b93 cpu/stm32: set CPU_HAS_BITBAND 2020-07-16 14:44:28 +02:00
055c43c878
cpu/stm32: enable flashpage feature for stm32f031k6 2020-07-16 11:15:30 +02:00
Bas Stottelaar
21f9afdb5b
Merge pull request #14318 from benpicco/cpu/stm32-TIMER_CHANNELS
cpu/stm32: use TIMER_CHANNEL_NUMOF for consistency
2020-06-24 15:32:22 +02:00
Benjamin Valentin
06cdd30fcb cpu/stm32: use TIMER_CHANNEL_NUMOF for consistency 2020-06-24 12:58:38 +02:00
f546c6238b
cpu/stm32: add support for stm32g4 2020-06-19 14:18:17 +02:00
Francisco Molina
0b8adb2d27
cpu/sam0-stm32/uart: rename tx buf size to UART_TXBUF_SIZE 2020-06-17 10:01:20 +02:00
Francisco Molina
3107993434
cpu/stm32: add non blocking uart
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2020-06-11 09:51:41 +02:00
Benjamin Valentin
0819f0eb39 cpu/stm32: implement reset to bootloader
The STM32 line of microcontrollers comes with a bootloader in the ROM.
It provides the option to flash the device firmware in DFU mode (USB)
or via UART or SPI.

To enter the bootloader we have to jump to a specific address in memory,
but before reset the CPU to make sure the system is in a known state.

This enables us to use the usb_board_reset module on all STM32 platforms.
2020-06-05 18:41:06 +02:00
c28477a4f0
Merge pull request #14096 from bergzand/pr/stm32_common/dma/optimize_hot_path
STM32_common/dma: Optimize the latency in the hot path
2020-06-02 16:01:27 +02:00