hugues
2f0ac9e820
cpu/stm32/periph/spi: use dma_stop for STM32s that need it
2020-08-19 11:25:34 +02:00
Francisco
cc954274a7
Merge pull request #14763 from hugueslarrive/cpu/stm32/vectors/vectors_f3
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cpu/stm32/vectors/vectors_f3: a small fix for STM32F334x8
2020-08-19 10:08:31 +02:00
Leandro Lanzieri
a64461cdad
cpu/esp_common: stdio_uart by default if there is no other
2020-08-19 10:00:35 +02:00
Leandro Lanzieri
67aec8392c
cpu/atmega_common: use stdio_uart only when no other is defined
2020-08-19 10:00:26 +02:00
Leandro Lanzieri
8f9ce7f81f
cpu/cc26x2_cc13x2: remove unnecessary pm.c
...
This CPU families already use the peripheral implementation of
cc26xx_cc13xx for PM.
2020-08-19 09:50:56 +02:00
benpicco
4a2d867339
Merge pull request #14749 from bergzand/pr/stm32/dynamic_spi_freqs
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stm32: Add support for arbitrary SPI clock rates
2020-08-18 17:57:30 +02:00
Benjamin Valentin
277452807b
cpu/esp_common: flash: implement write_page()
2020-08-18 17:25:40 +02:00
9d49a30560
stm32: Remove obsolete spi_divtable tool
2020-08-18 16:55:01 +02:00
b9d62e47d3
stm32: Add support for arbitrary SPI clock rates
2020-08-18 16:55:01 +02:00
benpicco
04df2bbd8a
Merge pull request #14779 from fjmolinas/pr_stm32f1_rtt_fixes
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cpu/stm32/f1/rtt: fixes and improvements
2020-08-18 16:07:00 +02:00
Francisco Molina
14d4d2aacb
cpu/stm32/f1/rtt: don't trigger callbacks if unset
2020-08-18 14:10:15 +02:00
Francisco Molina
0d60b3370a
cpu/stm32/f1/rtt: some fixes to rtt_set_alarm
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- disable alarm before setting a new one
- save cb and argument context before enabling the ISR
2020-08-18 13:43:10 +02:00
2f30aaaf06
cpu/cortexm_common: use mpu stack guard if DEVELHELP is enabled
2020-08-18 10:26:21 +02:00
benpicco
22d3bf7c51
Merge pull request #14594 from maribu/stm32-eth-cleanup
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cpu/stm32: Clean up / fix periph_eth
2020-08-17 21:16:27 +02:00
Marian Buschsieweke
90c59b1c6f
Merge pull request #14733 from benpicco/cpu/lpc23xx/rtc_cleanup
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cpu/lpc23xx: RTC: cleanup
2020-08-17 20:34:30 +02:00
Marian Buschsieweke
4fcf37c162
cpu/stm32/periph_eth: Handle lost & spurious IRQs
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Fixes https://github.com/RIOT-OS/RIOT/issues/13496
2020-08-17 20:30:16 +02:00
Marian Buschsieweke
8d8af31e39
driver/stm32_eth: Integrate into periph_eth
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The stm32_eth driver was build on top of the internal API periph_eth, which
was unused anywhere. (Additionally, with two obscure exceptions, no functions
where declared in headers, making them pretty hard to use anyway.)
The separation of the driver into two layers incurs overhead, but does not
result in cleaner structure or reuse of code. Thus, this artificial separation
was dropped.
2020-08-17 20:29:33 +02:00
Marian Buschsieweke
28ed07d6e3
cpu/stm32/periph_eth: zero-copy TX (-6 KiB RAM)
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The Ethernet DMA is capable of collecting a frame from multiple chunks, just
like the send function of the netdev interface passes. The send function was
rewritten to just set up the Ethernet DMA up to collect the outgoing frame
while sending. As a result, the send function blocks until the frame is
sent to keep control over the buffers.
This frees 6 KiB of RAM previously used for TX buffers.
2020-08-17 20:29:33 +02:00
Marian Buschsieweke
51fe77afa4
cpu/stm32/periph_eth: configurable buffer size
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1. Move buffer configuration from boards to cpu/stm32
2. Allow overwriting buffer configuration
- If the default configuration ever needs touching, this will be due to a
use case and should be done by the application rather than the board
3. Reduce default RX buffer size
- Now that handling of frames split up into multiple DMA descriptors works,
we can make use of this
Note: With the significantly smaller RX buffers the driver will now perform
much worse when receiving data at maximum throughput. But as long as frames
are small (which is to be expected for IoT or boarder gateway scenarios) the
performance should not be affected.
2020-08-17 20:29:29 +02:00
Marian Buschsieweke
932c311ee2
cpu/stm32/periph_eth: Fix RX logic
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If any incoming frame is bigger than a single DMA buffer, the Ethernet DMA will
split the content and use multiple DMA buffers instead. But only the DMA
descriptor of the last Ethernet frame segment will contain the frame length.
Previously, the frame length calculation, reassembly of the frame, and the
freeing of DMA descriptors was completely broken and only worked in case the
received frame was small enough to fit into one DMA buffer. This is now fixed,
so that smaller DMA buffers can safely be used now.
Additionally the interface was simplified: Previously two receive flavors were
implemented, with only one ever being used. None of those function was
public due to missing declarations in headers. The unused interface was
dropped and the remaining was streamlined to better fit the use case.
2020-08-17 20:28:49 +02:00
Marian Buschsieweke
35d46e6dc3
cpu/esp: Use API to access sched internals
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Replace access to `sched_active_task` and `sched_active_pid` with calls to
`thread_getpid()` and `thread_get_active()`.
2020-08-17 14:05:05 +02:00
Marian Buschsieweke
b657ebc39a
cpu/native: Don't access sched_active_*
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Replaced accesses to sched_active_* with API calls in C files
2020-08-17 12:16:08 +02:00
Marian Buschsieweke
c01ef33ccc
cpu/msp430_common: Don't access sched_active_*
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Replaced accesses to sched_active_* with API calls in C files
2020-08-17 12:16:07 +02:00
Marian Buschsieweke
ac394ce826
cpu/mips32r2_common: Don't access sched_active_*
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Replaced accesses to sched_active_* with API calls in C files
2020-08-17 12:16:07 +02:00
Marian Buschsieweke
346fb432ed
cpu/fe310: Don't access sched_active_*
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Replaced accesses to sched_active_* with API calls in C files
2020-08-17 12:16:07 +02:00
Marian Buschsieweke
aeedb3ad16
cpu/cortexm_common: Don't access sched_active_*
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Replaced accesses to sched_active_* with API calls in C files
2020-08-17 11:27:52 +02:00
Marian Buschsieweke
fa12d9ad52
cpu/atmega_common: Don't access sched_active_*
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Replaced accesses to sched_active_* with API calls in C files
2020-08-17 11:26:19 +02:00
Marian Buschsieweke
da4979963d
cpu/arm7_common: Don't access sched_active_*
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Replaced accesses to sched_active_* with API calls in C files
2020-08-17 11:22:03 +02:00
Benjamin Valentin
bdc43c245c
cpu/native: RTC: implement rtc_set_alarm()
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Use xtimer to simulate an RTC timer.
This allows to simulate software that makes use of `rtc_set_alarm()`
on native.
2020-08-16 23:28:30 +02:00
Benjamin Valentin
f0e77840dc
cpu/nrf52: spi_twi_irq add workaround for nRF52810 vendor file
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Either nRF52810 should define SPIM_COUNT 2 or nRF52805 should
define SPIM_COUNT 1.
But as it nRF52805 defines SPIM_COUNT 2 and nRF52810 defines SPIM_COUNT 1
even though both have a single SPI and a single, separate TWI peripheral.
Re-define SPIM_COUNT to 2 on nRF52810 as this is the easiest solution.
2020-08-16 23:26:17 +02:00
Benjamin Valentin
5ecf2e8bb1
cpu/nrf52: ensure PWM is present
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Not all members of the family have a PWM peripheral
2020-08-16 23:26:17 +02:00
Benjamin Valentin
899e97af30
cpu/nrf52: add definitions for remaining family members
2020-08-16 23:26:17 +02:00
hugues
7b3b10303b
cpu/stm32/vectors/vectors_f3: a small fix for STM32F334x8
2020-08-14 14:03:10 +02:00
Cenk Gündoğan
f64511ddb5
Merge pull request #14626 from leandrolanzieri/pr/kconfig/test_modules_kconfig
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kconfig: introduce migration test in CI
2020-08-13 14:11:00 +02:00
Benjamin Valentin
2509c206ee
cpu/lm4f120: GPIO: clear stale interrupt
2020-08-13 10:12:21 +02:00
7e411ec1b0
Merge pull request #14741 from fjmolinas/pr_fe310_configurable_rtt
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cpu/fe310: add unified rtt configuration
2020-08-12 18:36:15 +02:00
Francisco Molina
442b11d0ee
cpu/fe310: add unified rtt configuration
2020-08-12 14:46:59 +02:00
Leandro Lanzieri
7dc6639f59
cpu/cortexm_common: add default Kconfig configuration
2020-08-12 12:22:43 +02:00
Leandro Lanzieri
f4e651e26d
cpu/sam0_common: Add default Kconfig configuration
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The configuration file is included by samd21 so it is merged when using
Kconfig.
2020-08-12 12:22:42 +02:00
Leandro Lanzieri
b98527ef53
cpu: Add 'periph' module to Kconfig
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Select it from cortexm_common module as it is always needed.
2020-08-12 12:22:39 +02:00
Leandro Lanzieri
0ddd2886b7
cpu/sam0_common: add sam0_common_periph module to Kconfig
2020-08-12 12:22:39 +02:00
Leandro Lanzieri
2d53003ee2
cpu/cortexm_common: Model cortexm_common modules
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This models cortexm_common and cortexm_common_periph modules.
2020-08-12 12:22:39 +02:00
Leandro Lanzieri
4ad2180f81
kconfig: Add default modules' symbols
2020-08-12 12:22:38 +02:00
Francisco Molina
8ed8daa493
cpu/cc2538/timer: fix 32 bit timer reload value
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The interval load value was only set to 0xffff regardless of the counter
mode used which mad the 32bit timer apparently stop after 0xffff (it
would never reach values >0xffff).
When a GPTM is configured to one of the 32-bit modes, TAILR appears as a
32-bit register (the upper 16-bits correspond to the contents of the
GPTM Timer B Interval Load (TBILR) register). In a 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the
state of TBILR.
Thsi commit set the correct value for TAILR depending on the configured
timer mode.
2020-08-12 11:35:42 +02:00
benpicco
419ee52ddc
Merge pull request #14711 from benpicco/cpu/sam0_common/gpio-intermediate_irq
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cpu/sam0_common: GPIO: ignore stale interrupts
2020-08-11 16:32:57 +02:00
benpicco
ea42705637
Merge pull request #14564 from benpicco/cpu/stm32-bitarithm_test_and_clear
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cpu/stm32: GPIO: use bitarithm_test_and_clear()
2020-08-11 14:05:38 +02:00
benpicco
3ef906c841
Merge pull request #14563 from benpicco/cpu/sam0_common-bitarithm_test_and_clear
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cpu/sam0_common: GPIO: use bitarithm_test_and_clear()
2020-08-11 14:05:06 +02:00
Francisco
16f47fc893
Merge pull request #14502 from benpicco/cpu/sam0_common/flashpage_cleanup
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cpu/sam0_common: flashpage: clean up implementation
2020-08-10 08:21:49 +02:00
Marian Buschsieweke
7d9aed7f66
Merge pull request #14391 from benpicco/cpu/stm32-timer_periodic
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cpu/stm32: implement periph_timer_periodic
2020-08-10 07:58:27 +02:00
Benjamin Valentin
a0972c9e0c
cpu/stm32: implement periph_timer_periodic
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Seems like the Interrupt flag for a Capture/Compare channel gets set when
- the CC-value is reached
- the timer resets before the CC value is reached.
We only want the first event and ignore the second one. Unfortunately I did
not find a way to disable the second event type, so it is filtered in software.
That is we need to
- ignore the CC-interrupts when the COUNT register register is reset
- ignore the CC-interrupts > TOP value/ARR (auto-reload register)
2020-08-09 22:55:22 +02:00
Benjamin Valentin
91ad431e34
cpu/nrf52: fix nrf52811 vector definition
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SWI2 was missing - compare with vendor/nrf52811.h
2020-08-09 21:46:06 +02:00
Benjamin Valentin
4980cb7abe
cpu/nrf52: fix nrf52832 vector definition
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The CPU has 39 interrupt vectors and the FPU interrupt is the last one.
(Yes this MCU has an FPU).
Compare with vendor/nrf52.h
2020-08-09 21:46:06 +02:00
Benjamin Valentin
3f8bb169c6
cpu/nrf52: fix nrf52840 vector definition
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The CPU has 48 interrupt vectors and spi3 is the last one.
See vendor/nrf52840.h
2020-08-09 21:46:06 +02:00
Benjamin Valentin
ec67798cf0
cpu/nrf52: fix spi_twi_irq for nrf52805/10/11
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These smaller parts have SPI1 mapped to TWI0 (if SPI1 exists at all).
2020-08-09 21:46:06 +02:00
Benjamin Valentin
ca2b7e1952
cpu/nrf5x_common: UART: capture whole nrf52 lineup
2020-08-09 21:46:06 +02:00
Benjamin Valentin
1713dca711
cpu/nrf52: gpio: fix build for nrf52811
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We can use a more general conditional here.
2020-08-09 21:46:06 +02:00
Benjamin Valentin
2f236cb092
cpu/nrf52: only enable instruction cache if available
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The instruction cache is not available on all nrf52 MCUs.
2020-08-09 21:46:06 +02:00
Benjamin Valentin
ea2638dcac
cpu/nrf52: split up vector definition
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The interrupt vectors vary between each member of the family.
To retain sanity, split the vectors file up for each MCU.
2020-08-09 21:46:06 +02:00
Benjamin Valentin
307495985a
cpu/nrf52: not all parts have a FPU
2020-08-09 21:46:06 +02:00
Benjamin Valentin
7a9e68af96
cpu/nrf52: add vendor files for nrf52805/10/20/33
2020-08-09 21:46:06 +02:00
Marian Buschsieweke
234a720571
Merge pull request #14516 from benpicco/bitband_hw
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cortexm_common: fix check for bitbanding feature
2020-08-08 14:26:49 +02:00
Benjamin Valentin
0e22910c94
cpu/sam_common: set CPU_HAS_BITBAND
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- https://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11057-32-bit-Cortex-M3-Microcontroller-SAM3X-SAM3A_Datasheet.pdf
- http://ww1.microchip.com/downloads/en/DeviceDoc/Atmel-11100-32-bit%20Cortex-M4-Microcontroller-SAM4S_Datasheet.pdf
2020-08-08 12:44:11 +02:00
Benjamin Valentin
e886dad430
cpu/lpc1768: set CPU_HAS_BITBAND
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> Support for Cortex-M3 bit banding.
https://www.nxp.com/docs/en/data-sheet/LPC1769_68_67_66_65_64_63.pdf
2020-08-08 12:44:11 +02:00
Benjamin Valentin
225f56b5e6
cpu/lm4f120: set CPU_HAS_BITBAND
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> A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
> The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. A
https://www.mouser.com/datasheet/2/405/lm4f120h5qr-124014.pdf
2020-08-08 12:44:11 +02:00
Benjamin Valentin
fae0b00918
cpu/cc26x0: set CPU_HAS_BITBAND
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> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.
https://www.ti.com/lit/ug/swcu117i/swcu117i.pdf
2020-08-08 12:44:11 +02:00
Benjamin Valentin
098b37a7dc
cpu/cc26x2_cc13x2: set CPU_HAS_BITBAND
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> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.
https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf
2020-08-08 12:44:11 +02:00
Benjamin Valentin
b8d49fe627
cpu/cc2538: set CPU_HAS_BITBAND
2020-08-08 12:44:11 +02:00
Benjamin Valentin
848326bed6
cpu/lpc23xx: RTC: cleanup
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- reduce indentation
- sanitize logic in rtc_set_alarm()
- ILR register is clear-on-write, writing 0 has no effect
2020-08-07 19:25:38 +02:00
benpicco
4635be207b
Merge pull request #14726 from benpicco/riot_epoch
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drivers/periph_common: RTC: use RIOT_EPOCH as the RTC reset value
2020-08-07 19:07:28 +02:00
Leandro Lanzieri
6b52c53db3
Merge pull request #14614 from aabadie/pr/boards/hifive1_clock_kconfig
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boards/hifive1*: add kconfig options to configure the clock
2020-08-07 17:40:08 +02:00
Benjamin Valentin
97bf000bcd
cpu/stm32: use RIOT_EPOCH
2020-08-07 17:39:25 +02:00
Benjamin Valentin
69c436b891
cpu/ezr32wg: set CPU_HAS_BITBAND
2020-08-07 17:38:38 +02:00
benpicco
a455d74621
Merge pull request #14729 from gschorcht/cpu/esp32/vendor_dependeny_boarddir
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cpu/esp32: remove the dependency of vendor code on BOARDDIR
2020-08-07 17:03:40 +02:00
benpicco
cc1ffc8a4d
Merge pull request #13357 from benemorius/pr/efm32-letimer
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cpu/efm32/timer: add support for LETIMER
2020-08-07 17:03:01 +02:00
Gunar Schorcht
d19a1f5af5
cpu/esp32: remove the dependency of vendor code on BOARDDIR
2020-08-07 16:09:12 +02:00
benpicco
574676b150
Merge pull request #14700 from fjmolinas/to_cc2538_enhance_rtt
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cpu/cc2538: RTT: implement missing API functions
2020-08-07 15:11:53 +02:00
Benjamin Valentin
6d684ee748
cpu/lpc23xx: use RIOT_EPOCH
2020-08-07 13:24:58 +02:00
Benjamin Valentin
d02aa4a6b5
cpu/sam0_common: RTC: use RIOT_EPOCH
2020-08-07 13:24:10 +02:00
7acf81552a
boards/hifive1* cpu/fe310: improve clock customization
2020-08-06 15:59:34 +02:00
Benjamin Valentin
39d71ac671
cpu/sam0_common: GPIO: ignore interrupts when interrupts are disabled
...
If we disable an external interrupt, GPIO events that would generate an interrupt will still set the interrupt flag.
That means once we enable the interrupt again, a stale interrupt will be triggered.
This is surprising and probably not what the user wants, unfortunately the API documentation is not very clear about what to expect.
There is however no way to drop those intermediate interrupts with the current API.
Ignoring the events that occurred while the GPIO interrupt were disabled is probably the right (and expected) thing to.
2020-08-05 16:57:05 +02:00
789f10e816
cpu/msp430_common: increase THREAD_STACKSIZE_DEFAULT to 384
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Both tests/pthread_tls and tests/prng_sha256prng fail without this, but
other platforms run fine with their defaults. Lets consider the higher
value a better default.
2020-08-05 14:32:58 +02:00
4f233cd7ea
cpu: remove cc430
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The only board with this chipset was the chronos, which has been
removed.
2020-08-05 14:32:58 +02:00
038823c731
cpu/msp430_common/vendor/README.md: add some explanation
2020-08-05 14:32:58 +02:00
5a00e2e36c
cpu/msp430_common: use __stack for ISR stacks
2020-08-05 14:32:58 +02:00
aa2f500d51
cpu/msp430_common: update thread_stack_init to changed ABI
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The old mspgcc used R15-R12 for args 0-3. The newer MSP430 EABI uses
R12-15.
See https://www.ti.com/lit/an/slaa664/slaa664.pdf for more details.
2020-08-05 14:32:58 +02:00
909d740d37
cpu/msp430_common: bump msp430-gcc-support-files to 1.210
2020-08-05 14:32:58 +02:00
ef099f9d46
cpu/msp430_common: add NOPs to irq functions
...
They might not be necessary, but GCC warns if they're absent.
Thus let's pay the one or two extra instructions for silencing the
warnings.
2020-08-05 14:32:58 +02:00
08c50947cc
cpu/msp430_common: move newlib default module decl to Makefile.dep
2020-08-05 14:32:58 +02:00
fd335d30ee
cpu/msp430: re-create c11_atomics_compat_cpu.hpp using msp430-elf-gcc
2020-08-05 14:32:58 +02:00
10213057b1
cpu/msp430: update deps, move to Makefile.dep
2020-08-05 14:32:57 +02:00
260ec3666f
cpu/msp430: select newlib_nano module if newlib is used
2020-08-05 14:29:07 +02:00
8753457e45
cpu/msp430_common: use default newlib heap_stats
2020-08-05 14:29:07 +02:00
9db23b6c3d
cpu/cc430: update to new support headers
2020-08-05 14:29:07 +02:00
dbcf59f196
cpu/msp430: call newlib _init() in startup script
2020-08-05 14:29:07 +02:00
178e39afc2
cpu/msp430: remove obsolete stdio code
2020-08-05 14:29:07 +02:00
30cf61dd35
cpu/msp430: remove obsolete msp430 specific headers
2020-08-05 14:29:07 +02:00
a0aeeb5ff4
cpu/msp430: update to modern gcc & newlib
2020-08-05 14:29:00 +02:00
bf072bdd55
cpu/msp430_common: add msp430-gcc-support-files 1.208
2020-08-05 14:27:25 +02:00
0268a772ed
Revert "cpu/msp430_common: set top of heap for sbrk"
...
This reverts commit 55f433103b
2020-08-05 14:27:25 +02:00
5b6534e02d
Revert "cpu/msp430_common: add real malloc/free functions"
...
This reverts commit 419cedf58e
2020-08-05 14:27:25 +02:00
Benjamin Valentin
a8d5f13ad9
cpu/cc2538: rtt: allow to set alarm and overflow cb independently
...
Previously the setting the alarm would overwrite the overflow callback
and vice versa.
Since we can only set one alarm in hardware, always set the alarm to the
closest event of the two.
2020-08-04 16:22:44 +02:00
Benjamin Valentin
852fd7f531
cpu/cc2538: rtt: implement rtt_get_alarm()
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We can't read back the alarm, so just store it in a variable.
2020-08-04 16:21:19 +02:00
Benjamin Valentin
d7f722e98f
cpu/cc2538: rtt: implement rtt_set_counter()
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We can't set the hardware counter directly, so always add an offset.
2020-08-04 16:21:17 +02:00
Leandro Lanzieri
d7dbbb71ac
Merge pull request #14226 from benpicco/cpu/sam0_common/i2c_arbitrary_freqs
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cpu/sam0_common: i2c: fix BAUD handling & cleanup
2020-08-04 14:49:10 +02:00
Benjamin Valentin
1472d2095c
cpu/sam0_common: i2c: document frequency constraints
2020-08-04 12:13:28 +02:00
Benjamin Valentin
e560042488
cpu/sam0_common: flashpage: split RWWEE and normal functions
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Move common code into helper functions and extract the commands
that differ between normal and RWWEE page reading / writing.
This cuts down on `#ifdef` use.
2020-08-04 12:00:49 +02:00
Peter Kietzmann
6adf07caf0
Merge pull request #14672 from jia200x/pr/fix_cc2538_rssi
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cc2538: fix RSSI offset
2020-08-03 09:45:16 +02:00
Peter Kietzmann
c1f83aeac8
Merge pull request #14673 from jia200x/pr/fix_nrf_pow
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nrf802154: fix set_tx_power function
2020-08-02 15:19:51 +02:00
Benjamin Valentin
548f59d380
cpu/samd5x: remove RTC workaround
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This is no longer needed.
2020-07-31 22:00:09 +02:00
Benjamin Valentin
83a56ae666
cpu/sam0_common: merge RTC & RTT implementation
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The RTC and RTT share the same peripheral, so they can also
share the same code.
This is needed to integrate the Tamper Detection into common
RTC/RTT code.
2020-07-31 22:00:09 +02:00
Jose Alamos
5c824f6f12
nrf802154: fix set_tx_power function
2020-07-31 17:16:10 +02:00
Jose Alamos
519f8f4529
cc2538: fix RSSI offset
2020-07-31 16:08:04 +02:00
Francisco
7e6fee8260
Merge pull request #14615 from maribu/atmega-idle-stack-size
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cpu/atmega_common: Increase idle stack size with xtimer
2020-07-30 14:43:20 +02:00
Martine Lenders
5cd3ded485
Merge pull request #14649 from gschorcht/cpu/esp32/cleanu_cpp
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cpu/esp32: cleanup of C++ hacks
2020-07-29 11:20:44 +02:00
Francisco
9adc79f91a
Merge pull request #14562 from benpicco/cpu/cc2538-bitarithm_test_and_clear
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cpu/cc2538: GPIO: use bitarithm_test_and_clear()
2020-07-29 10:38:37 +02:00
Gunar Schorcht
2ed4486f21
cpu/esp32: cleanup of C++ hacks
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Since former ESP32 toolchain versions used POSIX threads, module `pthread` was required. The built-in `cxa_ctor_guards` had to be replaced since they used the `pthread_once` function for singleton objects initialization where the parameter `once` was of incompatible type with that provided by RIOT's `pthread` module. The current ESP32 toolchain version no longer uses POSIX threads. The dependency on module `pthread` as well as according C++ hacks can be removed.
2020-07-29 10:14:57 +02:00
Martine Lenders
b1bf8ab981
Merge pull request #14565 from bergzand/pr/sched/fix_retrigger
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sched: Prevent retriggering the scheduler interrupt during idle sleep
2020-07-28 22:11:25 +02:00
Marian Buschsieweke
9a14903066
Merge pull request #14326 from benpicco/cpu/sam0_common/uart_arithmetic
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cpu/sam0_common: UART: implement arithmetic BAUD mode
2020-07-28 19:43:25 +02:00
Martine Lenders
ab88a96a4a
Merge pull request #14638 from benpicco/cpu/native/async_read-cleanup
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cpu/native/async_read: close fds on cleanup
2020-07-28 18:39:41 +02:00
0b1a793dbe
Merge pull request #14624 from kaspar030/fix_msp430_thread_yield_higher
2020-07-28 16:32:30 +02:00
Benjamin Valentin
bd2e6c30e6
cpu/native/async_read: close fds on cleanup
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This was lost when moving to poll().
We need to close the fds on cleanup.
fixes #14636
2020-07-28 14:47:59 +02:00
1d46cf70eb
cpu/msp430_common: fix thread_yield_higher() when called in isr
2020-07-28 13:27:55 +02:00
Benjamin Valentin
274357d583
cpu/lpc23xx: GPIO: use bitarithm_test_and_clear()
2020-07-28 12:44:36 +02:00
Benjamin Valentin
08b3e2bd6b
cpu/cc2538: GPIO: use bitarithm_test_and_clear()
2020-07-28 12:44:23 +02:00
Benjamin Valentin
cc2a3c9fd3
cpu/sam0_common: GPIO: use bitarithm_test_and_clear()
2020-07-28 12:43:39 +02:00
Benjamin Valentin
9970c57cdf
cpu/stm32: GPIO: use bitarithm_test_and_clear()
2020-07-28 12:43:24 +02:00
benpicco
403b6b15c6
Merge pull request #14481 from maribu/cpp-fix-linking
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Makefile.{base,include}: Fix linking for C++ code in external modules
2020-07-28 12:42:14 +02:00
Benjamin Valentin
003c25b2e8
cpu/sam0_common: uart: document frequency constraints
2020-07-28 11:22:22 +02:00
Benjamin Valentin
e1f84de6c5
cpu/sam0_common: UART: simplify init sequence
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We don't need to read-modify-write the CTRLA register to disable
the UART.
The entire CTRLA register is re-written just a few lines below, so
we can just set it to 0 to disable the UART.
There is also no need to reset the UART since we re-write all config
registers in init.
2020-07-28 11:22:22 +02:00
Benjamin Valentin
28c1c502bc
cpu/sam0_common: UART: implement arithmetic BAUD mode
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SAMD20 does not implement a Fractional Baud mode, so we have to
implement Asynchronous Arithmetic mode.
2020-07-28 11:22:22 +02:00
benpicco
ecab75b529
Merge pull request #13632 from benpicco/cpu/sam0_common/uart-deinit
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drivers/periph/uart: add periph_uart_reconfigure feature & implementation for sam0
2020-07-28 11:12:19 +02:00
d59233baf1
Merge pull request #14556 from benpicco/bitarithm_test_and_clear
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core/bitarithm: add bitarithm_test_and_clear()
2020-07-28 10:11:47 +02:00
Benjamin Valentin
e6f33fc436
cpu/sam0_common: uart: implement the periph_uart_reconfigure feature
2020-07-28 10:10:15 +02:00
Benjamin Valentin
62dbb21f19
cpu/sam0_common: UART move pin configuration to function
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Makes the init code easier to read.
2020-07-28 10:10:15 +02:00
benpicco
22e9ba12a3
Merge pull request #14598 from maribu/avr-cpp
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cpu/atmega_common: Provide C++ support (without libstdc++)
2020-07-27 17:41:31 +02:00
Marian Buschsieweke
040bad0425
cpu/atmega_common: increase stack size with xtimer
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If a timer triggers while the idle thread is running, previously a stack
overflow was triggered. This commit increases the idle threads stack size if
xtimer is used.
2020-07-27 16:52:36 +02:00
millotp
69858916c7
boards: enable CAN bus on nucleo-f446re & nucleo-f446ze
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Changed the pinout for the CAN bus:
CAN RX: PB8
CAN TX: PB9
And added periph_can to FEATURES_PROVIDED and to Kconfig files
2020-07-27 14:36:29 +02:00
Marian Buschsieweke
53375f04bf
cpu/stm32/periph_eth: Optimize / fix flush
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- Added missing wait for TX flush
- Grouped access to the same registers of the Ethernet PHY to reduce accesses.
(The compiler won't optimize accesses to `volatile`, as defined in the C
standard.)
2020-07-26 22:12:03 +02:00
Marian Buschsieweke
a5dbec33d9
cpu/stm32/periph_eth: Cleanup & fix DMA descriptor
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- Add missing `volatile` to DMA descriptor, as memory is also accessed by the
DMA without knowledge of the compiler
- Dropped `__attribute__((packed))` from DMA descriptor
- The DMA descriptor fields need to be aligned on word boundries to
properly function
- The compiler can now more efficiently access the fields (safes ~300 B ROM)
- Moved the DMA descriptor struct and the flags to `periph_cpu.h`
- This allows Doxygen documentation being build for it
- Those types and fields are needed for a future PTP implementation
- Renamed DMA descriptor flags
- They now reflect to which field in the DMA descriptor they refer to, so
that confusion is avoided
- Added documentation to the DMA descriptor and the corresponding flags
2020-07-26 22:12:03 +02:00
Benjamin Valentin
4df36cbfda
cpu/sam0_common: i2c: improve readability of baud rate calculation
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Use variables to represent fSCL an fGCLK to make the baud rate calculation
more readable.
2020-07-25 15:14:55 +02:00
Benjamin Valentin
2fb0d9061f
cpu/sam0_common: i2c: fix High Speed
2020-07-25 15:14:55 +02:00
Benjamin Valentin
7269dc4e3a
cpu/sam0_common: i2c: allow arbitrary I2C frequencies
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The Atmel I2C peripheral supports arbitrary I2C frequencies.
Since the `i2c_speed_t` enum just encodes the raw frequency values,
we can just use them in the peripheral definition.
We just have to remove the switch-case block that will generate an error
for values outside of `i2c_speed_t`.
2020-07-25 15:14:55 +02:00
42eb044ec6
Merge pull request #14482 from hugueslarrive/cpu/stm32/periph/pwm
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cpu/stm32/periph/pwm: some bugfixes...
2020-07-24 21:05:57 +02:00
Marian Buschsieweke
7b49310147
cpu/atmega_common: Enable cpp feature
2020-07-24 15:22:34 +02:00
Marian Buschsieweke
7d4911e3ad
cpu/native/Kconfig: Select HAS_LIBSTDCPP
2020-07-23 20:34:20 +02:00
Marian Buschsieweke
c6df3ad643
cpu/arm7_common/Kconfig: Select HAS_LIBSTDCPP
2020-07-23 20:30:26 +02:00
Marian Buschsieweke
d15606908a
cpu/mips32r2_common/Kconfig: Select HAS_LIBSTDCPP
2020-07-23 20:28:32 +02:00
Marian Buschsieweke
f8b7c899f8
cpu/esp_common: Allows use feature cpp
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The vendor code uses C++ code, thus, C++ support needs to be enabled in any
case.
2020-07-23 20:18:33 +02:00
benpicco
f3bce19646
Merge pull request #14503 from maribu/cpp-feature
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build system: Add libstdcpp feature and doc
2020-07-23 19:05:10 +02:00
107356ec5d
Merge pull request #14575 from gschorcht/cpu/stm32/fix_gpio_definition
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cpu/stm32: GPIO ports definition fix
2020-07-23 12:24:44 +02:00
56f9a4a686
Merge pull request #14577 from fjmolinas/pr_cc2538_uart_write_synchronous
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cpu/cc2538/uart: uart_write wait for all bytes to be sent
2020-07-22 14:51:50 +02:00
Francisco Molina
da171f2254
cpu/cc2538/uart: uart_write wait for all bytes to be sent
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uart_write should block until all bytes are sent out, so wait for
transmit fifo to empty before returning.
2020-07-22 12:56:12 +02:00
Gunar Schorcht
044d08d599
cpu/stm32: GPIO ports definition fix
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The available GPIO ports may also differ within a family. Therefore, the vendor definitions GPIO* are used instad of CPU_FAM_STM definitions to determine which ports are available for a certain MCU.
2020-07-22 09:13:52 +02:00
Benjamin Valentin
464dc63f08
cpu/arm7_common: add __ARM_FEATURE_CLZ feature test
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The feature test macro should work on all ARM CPUs supported by gcc.
2020-07-21 16:03:59 +02:00
Benjamin Valentin
a8904edd7d
core/bitarithm: add bitarithm_test_and_clear()
2020-07-21 16:03:59 +02:00
185f703c23
Merge pull request #14163 from aabadie/pr/cpu/stm32g0
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cpu/stm32g0: add basic support + add nucleo-g070rb board
2020-07-21 14:53:59 +02:00
b7219d68f4
Merge pull request #12428 from benpicco/native_poll
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native/async_read: use poll() instead of select()
2020-07-21 14:01:32 +02:00
fc1d642113
cpu/cortexm_init: add specific case for stm32g0 svcall irq
2020-07-21 12:45:25 +02:00
dada52ecd2
cpu/stm32: add stm32g0 support
2020-07-21 12:45:25 +02:00
0b549c6e0c
Merge pull request #14152 from aabadie/pr/pkg/stm32cube
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pkg/stm32cmsis: retrieve STM32 CMSIS header from a package
2020-07-21 12:27:19 +02:00
47e2885f80
cpu/native: async_read: add native_async_read_add_int_handler()
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fcntl(fd, F_SETOWN, getpid()); doesn't seem to work on Linux
to get generate a signal when an event on the GPIO fd occurs.
So fall back to the same method as on OS X and call poll() in
a child process.
2020-07-21 11:50:18 +02:00
a274ea45fc
cpu/native: async_read: rewrite select() call to poll()
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select() can not listen to POLLPRI events which are used by the
Kernel's GPIO API.
In preparation for that, rewrite async_read() to use poll() instead
of select().
2020-07-21 11:50:18 +02:00
0eb66a429f
cortexm_common: Clear PendSV request after idle sleep
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The PendSV interrupt is used to request a scheduling operation. An
interrupt during the idle sleep can re-request the PendSV interrupt,
while the PendSV is still busy scheduling the next thread. This clears
the request after sleep to prevent triggering an extra PendSV interrupt
after the current PendSV handler finished.
2020-07-21 11:23:49 +02:00
f013be5507
Merge pull request #14497 from aabadie/pr/drivers/makefile_dep_cleanup
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drivers/Makefile.dep: remove inappropriate use of FEATURES_PROVIDED for rtt_rtc
2020-07-20 13:04:59 +02:00
Leandro Lanzieri
64f75bcc30
cpu/saml21: Add Kconfig symbols
2020-07-16 21:29:46 +02:00
4da79fa0ca
Merge pull request #14471 from leandrolanzieri/pr/kconfig/lpc2387_boards_symbols
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boards/lpc2387-based: Model features in Kconfig
2020-07-16 21:25:00 +02:00
3b778451e1
Merge pull request #14485 from leandrolanzieri/pr/kconfig/saml1x_based_symbols
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boards/saml1x-based: Model features in Kconfig
2020-07-16 21:04:22 +02:00
Leandro Lanzieri
110793be0c
cpu/lpc23xx: Add Kconfig symbols
2020-07-16 19:03:38 +02:00
Leandro Lanzieri
c71c2b79a7
cpu/arm7_common: Add Kconfig symbols
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HAS_ARCH_ARM features now is moved to Kconfig.features as it is being
used by multiple architectures.
2020-07-16 19:03:38 +02:00
a20d663086
Merge pull request #14470 from leandrolanzieri/pr/kconfig/lpc1768_boards_symbols
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boards/lpc1768-based: Model features in Kconfig
2020-07-16 18:59:55 +02:00
d0fb8d727a
Merge pull request #14539 from aabadie/pr/cpu/lpc2387_rename
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cpu/lpc2387: rename to lpc23xx
2020-07-16 18:38:47 +02:00
Leandro Lanzieri
38636a8089
cpu/saml1x: Add Kconfig symbols
2020-07-16 18:09:59 +02:00
Leandro Lanzieri
84de2d8f7b
cpu/saml1x: Specify CPU_FAM only in Makefile.features
2020-07-16 18:09:58 +02:00
e246e7ed2a
Merge pull request #14538 from leandrolanzieri/pr/kconfig/native_symbols
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boards/native: Model features in Kconfig
2020-07-16 18:04:42 +02:00
dea506a719
cpu/stm32wb: define missing IMR bit in CMSIS
2020-07-16 17:35:50 +02:00
1a095b36fa
cpu/stm32: adapt UART driver for stm32l4r5 cpu line
2020-07-16 17:35:49 +02:00
8e87dedbce
cpu/stm32: remove not needed CMSIS vendor headers
2020-07-16 17:35:49 +02:00
f21440b176
cpu/stm32: use CMSIS headers from the stm32cmsis package
2020-07-16 17:35:48 +02:00
1f0a3a6bae
cpu/cortexm_common: add special case for SVC interrupt configuration
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by default stm32f0/l0/l1 families simply call the interrupt enum SVC_IRQn
2020-07-16 17:35:48 +02:00
def5f80998
Merge pull request #14477 from leandrolanzieri/pr/kconfig/sam3_boards_symbols
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boards/sam3-based: Model features in Kconfig
2020-07-16 17:07:03 +02:00
0a699e87c7
cpu/lpc23xx: rename remaining occurrences of lpc2387
2020-07-16 17:01:10 +02:00
46a053e674
cpu/lpc23xx: rename Doxygen group
2020-07-16 17:01:10 +02:00
829b16b472
cpu/lpc23xx: rename lpc2387 to lpc23xx
2020-07-16 17:01:10 +02:00
a4129d0f8f
Merge pull request #14483 from leandrolanzieri/pr/kconfig/samd5x_based_symbols
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boards/same54-xpro: Model features in Kconfig
2020-07-16 16:38:21 +02:00
Leandro Lanzieri
8e5c0f3f84
cpu/lpc1768: Add Kconfig symbols
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Also specify CPU_FAM in Makefile.features
2020-07-16 15:39:02 +02:00
Leandro Lanzieri
44be83e4bb
cpu/sam3: Add Kconfig symbols
2020-07-16 15:35:23 +02:00
Martine Lenders
ea8e867611
Merge pull request #14534 from bergzand/pr/cortexm/irq_during_idle
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cortexm_common: disable IRQ during thread_sched_idle
2020-07-16 15:35:14 +02:00
Leandro Lanzieri
1c9a95e955
cpu/samd5x: Add Kconfig symbols
2020-07-16 15:33:29 +02:00
15110af51c
Merge pull request #14475 from leandrolanzieri/pr/kconfig/mips32r2_boards_symbols
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boards/mips32r2-based: Model features in Kconfig
2020-07-16 15:14:29 +02:00
Benjamin Valentin
f53ae74269
cpu/kinetis: set CPU_HAS_BITBAND
2020-07-16 14:44:28 +02:00
Benjamin Valentin
8f36c88b93
cpu/stm32: set CPU_HAS_BITBAND
2020-07-16 14:44:28 +02:00
Benjamin Valentin
b716419462
cpu/efm32: set CPU_HAS_BITBAND
2020-07-16 14:44:28 +02:00
Benjamin Valentin
95ec5890b0
cortexm_common: fix bit-banding check
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Not all MCUs ≥ Cortex-M3 provide the Bit-Banding feature.
It is up to the manufacturer to implement it.
Instead, rely on the CPU_HAS_BITBAND being set in `periph_cpu.h`.
2020-07-16 14:44:28 +02:00
Leandro Lanzieri
64970ab131
cpu/native: Add Kconfig symbols
2020-07-16 13:53:45 +02:00
Leandro Lanzieri
52b31b5fce
cpu/lm4f120: Add Kconfig symbols
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Also specify CPU_FAM in Makefile.features
2020-07-16 13:23:30 +02:00
Leandro Lanzieri
710c21805d
cpu/mips_pic32mz: Add Kconfig symbols
2020-07-16 13:20:05 +02:00
Leandro Lanzieri
6091c31bd6
cpu/mips_pic32mx: Add Kconfig symbols
2020-07-16 13:20:05 +02:00
Leandro Lanzieri
c1b25655fd
cpu/mips_pic32_common: Add Kconfig symbols
2020-07-16 13:20:04 +02:00
Leandro Lanzieri
ea3166e08e
cpu/mips32r2_common: Add Kconfig symbols
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Also this moves the specification of CPU_ARCH to the common folder
2020-07-16 13:20:01 +02:00
8046a74e50
cpu/stm32: model features in Kconfig
2020-07-16 11:34:02 +02:00
