RIOT-OS/RIOT
RIOT-OS/RIOT
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28,870 Commits 40 Branches 189 Tags 263 MiB
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5401 Commits

Author SHA1 Message Date
Alexandre Abadie
3b0510f9bc
Merge pull request #14077 from maribu/esp32-external-board 
cpu/esp*: Allow compilation with external boards
 2020-05-14 21:16:54 +02:00
Francisco
1f9d299492
Merge pull request #13196 from HendrikVE/shell-readline-refactor 
sys/shell: refactor readline function
 2020-05-14 15:32:45 +02:00
Marian Buschsieweke
fc28ba5c08
cpu/esp8266: Allow compilation with external boards 
Replace `$(RIOTBOARD)/$(BOARD)` with `$(BOARDDIR)`, which also works for
external boards.
 2020-05-14 13:35:51 +02:00
Marian Buschsieweke
1dbcdd3d4b
cpu/esp32: Allow compilation with external boards 
Replace `$(RIOTBOARD)/$(BOARD)` with `$(BOARDDIR)`, which also works for
external boards.
 2020-05-14 13:32:19 +02:00
Kees Bakker
5ef4b1843a
Merge pull request #14032 from benpicco/cpu/sam0_common-rtc_cleanup 2020-05-13 22:54:31 +02:00
Kaspar Schleiser
da2230df48
Merge pull request #13999 from fjmolinas/pr_cortexm_inline_irq 
cpu/cortexm_common: add inlined header only def for irq_%
 2020-05-12 21:15:57 +02:00
Gunar Schorcht
fef3c101b7 Revert "cpu/esp_common: fix dependency of flash target on ELF file" 
This reverts commit d0cc955394.
 2020-05-12 18:07:48 +02:00
Francisco Molina
b5e4224a6f
cpu/cortexm_common: remove special cortexm_sleep handle for stm32l152re 
__set_PRIMASK(state) had been directly inlined to avoid a hardfault that
occured when branching after waking up from sleep with DBG_STANDBY,
DBG_STOP or DBG_SLEEP set in DBG_CR.

The hardfault occured when returning from the branch to irq_restore,
since the function is now inlined the branch does not happen either.

Refer to #14015 for more details.
 2020-05-12 16:37:34 +02:00
Francisco Molina
4ad3164599
cpu/cortexm_common/irq_arch: fix irq_enable return type 2020-05-12 16:37:34 +02:00
Francisco Molina
cb5cbe7431
cpu/cortexm_common: add inlined header only def for irq_% 
irq_% are not inlined by the compiler which leads to it branching
to a function that actually implement a single machine instruction.

Inlining these functions makes the call more efficient as well as
saving some bytes in ROM.
 2020-05-12 16:37:34 +02:00
Benjamin Valentin
20a044c956 cpu/nrf52: fix nrf52811 interrupt vector table 
SPI1 and TWI0 share the same IRQ, not SPI1 and TWI1
 2020-05-12 15:10:06 +02:00
Benjamin Valentin
d53bc7bf73 cpu/nrf52: add peripherals.h vendor files 
Those make our lives much easier.
 2020-05-12 14:52:06 +02:00
Benjamin Valentin
fb2f2c456f cpu/nrf52: add nrf52811 vendor files 2020-05-12 14:49:26 +02:00
Philipp Blum
35dcf637f2 cpu/nrf52: add support for nrf52811 2020-05-10 17:10:33 +02:00
benpicco
0bbc86a379
Merge pull request #14041 from gschorcht/cpu/esp/fix_make_flash_dependency 
cpu/esp_common: fix the dependency of the flash image on the ELF file
 2020-05-08 11:55:14 +02:00
Gunar Schorcht
d0cc955394 cpu/esp_common: fix dependency of flash target on ELF file 
Flashing an ESP board first requires the creation of a flash image from the ELF file.  This is realized in the `preflash` target. However, the `preflash` target only depends on the variable `BUILD_BEFORE_FLASH` but on the ELF file. Therefore, the variable `BUILD_BEFORE_FLASH` must be set to the ELF file to ensure that when using multiple make processes, the compilation of the ELF file is completed before the flash image is created.
 2020-05-08 11:03:39 +02:00
Marian Buschsieweke
0fe24e1c8b
Merge pull request #13903 from benpicco/cpu/lpc2387/timer_pclk_scale 
cpu/lpc2387: timer: use lpc2387_pclk_scale()
 2020-05-07 22:04:14 +02:00
fabian18
a3a1c160ee mtd: Change API to return 0 on success 
Returning the number of bytes written/read could return a negative integer
because a uint32_t is expected for the length in read()/write() operations.
 2020-05-06 20:24:27 +02:00
Francisco Molina
bd3eff3537 cpu/esp32: switch from O2 to Os 
In #12955 optimization was switched to O2 because with the '-Os'
option, the ESP32 hangs sporadically in 'tests/bench*' if
interrupts where disabled too early by benchmark tests.

Since it hasn't been reproduced since and in #13196 O2 was causing
un-explained hardfaults, since the aforementioned issue could not
be reproduced we switch back to Os by removing O2, as Os will be
used by default.
 2020-05-06 18:46:43 +02:00
Benjamin Valentin
5481d8c73a cpu/sam0_common: clean up formatting 
Make the code nicer to read.
 2020-05-06 14:11:47 +02:00
Benjamin Valentin
e93c9a82f1 cpu/sam0_common: RTC INTFLAG are clear on write 
Writing a 1 bit clears the interrupt flag, writing with |= is thus
uneccecary (and actually an error as this would clear *all* flags).

This cleanup was already done for rtt.c, but rtc.c missed out.
 2020-05-06 14:05:12 +02:00
Francisco
cea0d1c532
Merge pull request #13421 from benpicco/cpu/sam0_common/i2c-deinit 
drivers/periph/i2c: add periph_i2c_reconfigure feature & implementation for sam0
 2020-05-05 19:09:47 +02:00
Alexandre Abadie
5773db93f8
Merge pull request #14025 from fjmolinas/pr_nrf5x_rtt_conf 
boards/common/nrf5x: add configurable RTT_FREQUENCY
 2020-05-05 17:46:05 +02:00
Benjamin Valentin
8c502322f4 cpu/sam0_common: i2c: implement the periph_i2c_reconfigure feature 
This adds sam0 implementations for

 - i2c_init_pins()
 - i2c_deinit_pins()
 - i2c_pin_sda()
 - i2c_pin_scl()
 2020-05-05 16:12:19 +02:00
Francisco Molina
409185c5ce
boards/common/nrf5x: add configurable RTT_FREQUENCY 
Adds: RTT_MAX_FREQUENCY, RTT_MIN_FREQUENCY & RTT_CLOCK_FREQUENCY
 2020-05-05 14:52:55 +02:00
Alexandre Abadie
cab264a056
cpu/lm4f120: fix invalid doxygen group name 2020-05-05 14:08:32 +02:00
Semjon Kerner
cb228a44f2
Merge pull request #14002 from PeterKietzmann/pr_nrf5x_hwrng_biascorr 
cpu/nrf5x_common: enable bias correction in hwrng
 2020-05-05 13:40:15 +02:00
benpicco
3c03394e1e
Merge pull request #13820 from francois-berder/pic32-gpio-irq 
cpu: mips_pic32_common: Implement GPIO IRQ
 2020-05-04 18:36:48 +02:00
Marian Buschsieweke
ac246cfd10
cpu/msp430_common: Fix missing include 2020-05-04 10:58:36 +02:00
benpicco
fbae0a1117
Merge pull request #13901 from benpicco/cpu/sam0_common/timer_flex_freq 
cpu/sam0_common: timer: don't ignore frequency in timer_init()
 2020-05-04 02:56:01 +02:00
benpicco
fab87d903c
Merge pull request #13991 from btcven/2020_04_30-osc 
cc26x2_cc13x2: add oscillator switching functions
 2020-05-02 22:46:03 +02:00
Dylan Laduranty
57c1a49a82
Merge pull request #13957 from benpicco/cpu/samd21-pwm_flex 
cpu/samd21: PWM don't hard-code number of channels to 3
 2020-05-02 20:52:56 +02:00
Martine Lenders
ad89680c40
Merge pull request #14004 from gschorcht/cpu/esp32/fix_newlib_nano_printf_float 
cpu/esp32: fix printf for float with newlib-nano
 2020-05-02 20:43:00 +02:00
Dylan Laduranty
76870721fe
Merge pull request #13965 from benpicco/cpu/sam0_common/periph/dac 
cpu/sam0_common: implement periph/dac
 2020-05-02 20:34:40 +02:00
Jean Pierre Dudey
4bf6a4db04
cc26x2_cc13x2: separate arrays with newline 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-05-02 13:25:41 -05:00
Jean Pierre Dudey
a66c693ad5
cc26x2_cc13x2: add oscillator switching functions 
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-05-02 13:25:41 -05:00
Jean Pierre Dudey
0aeed80eb0
cc26xx_cc13xx: add ROM Hard-API 
This is needed to switch the SCLK_HF source clock safely.

Note: these functions work on cc26x2_cc13x2 and cc26x0, but special care
needs to be taken when calling on cc26x0 some of these functions, as
ADDI_SEM needs to be taken.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-05-02 13:25:41 -05:00
Francois Berder
8db01ab9a0 cpu: mips_pic32_common: Implement GPIO IRQ 
Signed-off-by: Francois Berder <18538310+francois-berder@users.noreply.github.com>
 2020-05-02 17:59:17 +01:00
Benjamin Valentin
bfb3d52a63 cpu/sam0_common: implement periph/dac 
The sam0 MCUs all have a DAC peripheral.
The DAC has a resulution of 10 or 12 bits and can have one or two
output channels.

The output pins are always hard-wired to PA2 for DAC0 and PA5 for DAC1
if it exists.

On the same54-xpro I would only get a max value of ~1V when using the
internal reference, so I configured it to use an external voltage reference.

The external reference pin is hard-wired to PA3, so you'll have to connect
that to 3.3V to get results.
 2020-05-02 18:31:55 +02:00
Gunar Schorcht
5fbf74b203 cpu/esp32: fix printf for float with newlib-nano 2020-05-02 16:56:29 +02:00
PeterKietzmann
dd2d6b174e cpu/nrf5x_common: enable bias correction in hwrng 2020-05-01 17:04:36 +02:00
Benjamin Valentin
c05984b341 cpu/sam0_common: timer: don't ignore frequency in timer_init() 
Now that we can query the GCLK frequency at run-time, there is no need
to implicitely hard-code the timer frequency in the config struct anymore.
 2020-05-01 16:44:06 +02:00
benpicco
99e8b04921
Merge pull request #13812 from gschorcht/cpu/esp32/fix_newlib_nano 
cpu/esp32: use module newlib_nano
 2020-05-01 14:40:02 +02:00
benpicco
4150afea00
Merge pull request #13749 from gschorcht/cpu/esp32/periph_rtt 
cpu/esp32: replace RTC implementation by RTT implementation
 2020-05-01 14:14:01 +02:00
benpicco
c95e4c3b9e
Merge pull request #13816 from btcven/2020_04_02-setup-trim-device 
cc26x2_cc13x2: trim device registers on `cpu_init`.
 2020-05-01 14:09:08 +02:00
Benjamin Valentin
89a145ab0c cpu/lpc2387: clocks: minor style fix 2020-04-30 20:43:41 +02:00
Benjamin Valentin
c262c91561 cpu/lpc2387: PM: enable SLEEP & POWERDOWN mode 
We have to re-init PLL (and Flash) after wake from those modes.
 2020-04-30 20:43:41 +02:00
Benjamin Valentin
3b257f9a5a cpu/lpc2387: export functions to init PLL & MAM 
Those functions are needed after wake from lower sleep modes.
 2020-04-30 20:43:41 +02:00
Jean Pierre Dudey
951a99dba3
cc26x2_cc13x2: add setup_trim_device function 
This function trims the necessary registers for the device to operate
normally.

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:32:58 -05:00
Jean Pierre Dudey
dc1d2ace42
cc26xx_cc13xx: add ADI3 and masked access 
- Added ADI instruction offsets
- Added register banks and address bases for masked access (writes).

Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
 2020-04-29 18:32:58 -05:00