The CoAP thread stack size needs to be the same as the main
thread stack size to accommodate the EDHOC stack requirements.
This was lost when moving to the common CoAP server code.
The `Makefile.ci` was intended to be read and generated by command
line utilities and the contents should look exactly like this:
```
BOARD_INSUFFICIENT_MEMORY += \
board_a \
board_b \
... \
#
```
No fancy schmancy, no `include`, no nothing. This fixes the format.
This pulls in embedded-nal 0.7 implementations, and (on both crates)
alterations that decouple riot-wrappers from riot-sys and simplify build
system integration, and do away with the need for passing
RIOT_USEMODULE.
The constants BIG_ENDIAN etc. were not consistently defined. This
bug was not caught by the unit tests, as the preprocessor would
treat undefined macros as being `0` in numeric comparisons, hence
the following test did select the correct implementation:
```C
#if BYTE_ORDER == LITTLE_ENDIAN
/* correct implementation for all currently supported boards */
#endif
```
This adds now an explicit test to the unit tests to ensure that the
magic numbers are consistently the correct values. Hence, this bug
should no longer be able to sneak in.
Co-authored-by: Teufelchen <9516484+Teufelchen1@users.noreply.github.com>
Back when specific control of the Rust version used with RIOT was
needed, CARGO_CHANNEL was added to explicitly set the Rust version with
consideration for CI special cases.
Rust's mechansims of selecting a toolchain can be used instead now.
When it is difficult to navigate a function, it is overdue to split
it up :D
Also, no need to test for feature `gpio_ll_irq` in `test_irq()` *and*
before calling `test_irq()`.
- Move common code for USART (shared SPI / UART peripheral) to its
own file and allow sharing the USART peripheral to provide both
UART and SPI in round-robin fashion.
- Configure both UART and SPI bus via a `struct` in the board's
`periph_conf.h`
- this allows allocating the two UARTs as needed by the use case
- since both USARTs signals have a fixed connection to a single
GPIO, most configuration is moved to the CPU
- the board now only needs to decide which bus is provided by
which USART
Note: Sharing an USART used as UART requires cooperation from the app:
- If the UART is used in TX-only mode (no RX callback), the driver
will release the USART while not sending
- If the UART is used to also receive, the application needs to power
the UART down while not expecting something to send. An
`spi_acquire()` will be blocked while the UART is powered up.
The documentation on the state `GPIO_DISCONNECT` was a bit vague. The
API doc said it should disconnect the GPIO from all peripherals, the
test also tested them for being electrically disconnected.
The documentation in both the test and the API is extended to point out
that a GPIO indeed SHOULD be in high impedance state, but that user
MUST NOT expect that this requested is honored by every implementation
and for every GPIO pin.
In the test it is also pointed out that failing the test for a GPIO
in the `GPIO_DISCONNECT` state being electrically disconnected is for
some pins expected, and that the test should be just run again with
different GPIOs. The test intentionally tests for a feature not provided
by every GPIO pin rather than warning on a failure: The effort to just
flash and run the test again with different GPIOs is relatively low, but
it does confirm correct behavior of the API.
When using level triggered IRQs, a new IRQ flag may already have been
set while the IRQ callback is executed. Hence, we cannot just toggle
the output, but rather should drive it low/high for a level trigger on
high/low.
Also test `gpio_ll_query_conf()` for the disconnected state as well.
The default pin config is only a place holder anyway. But if it is
invalid at least on AVR most of the firmware is considered unreachable.
This updates the default GPIO config to something that should look
plausible to the compiler for all MCUs supporting GPIO LL, so that
ROM and RAM size in the CI start making sense.
Printing the newline after the state was printed is not optional.
This also moves the call to `gpio_ll_print_conf()` and `puts("")` to
a static function to safe enough ROM so that this still can be flashed
on `nucleo-l011k4`.
This commit optimizes the `gpio_conf_t` type in the following
regards:
- The "base" `gpio_conf_t` is stripped from members that only some
platforms support, e.g. drive strength, slew rate, and disabling of
the Schmitt Trigger are no longer universally available but
platform-specific extensions
- The `gpio_conf_t` is now crammed into a bit-field that is 8 bit or
16 bit wide. This allows for storing lots of them e.g. in
`driver_foo_params_t` or `uart_conf_t` etc.
- A `union` of the `struct` with bit-field members and a `bits` is used
to allow accessing all bits in a simple C statement and to ensure
alignment for efficient handling of the type
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Also the LF is display inside the [...].
Now it is more obvious what characters came in on the RX port of the UART.
Here is an example:
2024-01-20 20:57:41,368 # send 1 ati
2024-01-20 20:57:41,368 # UART_DEV(1) TX: ati
> 2024-01-20 20:57:41,393 # Success: UART_DEV(1) RX: [ati\r\r\n]
2024-01-20 20:57:41,398 # Success: UART_DEV(1) RX: [SARA-N310-00X-00\r\n]
2024-01-20 20:57:41,399 # Success: UART_DEV(1) RX: [\r\n]
2024-01-20 20:57:41,399 # Success: UART_DEV(1) RX: [OK\r\n]
This application uses `soft_uart` to bit-bang the name of a number of
configured GPIO pins via said pins at 9600 Bd. This way attaching an
USB UART bridge to one pin at a time easily reveals which MCU GPIO
pin a given pin on a board corresponds to. This is useful when no
schematic and no silkscreen labeling is available, or when the
information is misleading or outright incorrect (looking at the
E180-ZG120B-TB).
Reverts the type changes for the array size variables, as `size_t` is needed
in the function calls `fib_get_next_hop` and `fib_get_destination_set`.
Fixes 475a55136a
The CC2538-CC2592-DK is one of the few readily available and
affordable boards featuring a legacy CC2538 MCU. This should make
maintaining RIOT support for that legacy MCU more affordable :-)
- Added helper function to avoid 'format-truncation' warning
- Changed all `size_t` types to `unsigned`
- Changed function names from `_FIB_` to `_fib_`
- the timeout computation for the spurious IRQ test confused numerator
and denominator in a fraction
- the timeout offset between timer channels was hardcoded to 5000 from
when the timer was only tested with 1 MHz as frequency
- This resulted in slooooow test runs when running at slow
frequencies
- fix overflow handling in the spinning wait
- likely this would never overflow anyway assuming that
`timer_init()` resets the counter value, but let's not rely on
this and just fix the bug for good
If the feature periph_timer_query_freqs is provided, use the
corresponding function to iterate over all supported frequencies to
increase test coverage.
This test sporadically failed on multiple machines compiled with both
GNU and LLVM toolchains. To not waste more CI time by sporadically
failing unrelated CI runs, let's disable the test for now.
- Detect when the same timer is used by `ztimer` (pulled in as
dependency for a peripheral driver, e.g. `periph_adc` on STM32F3) and
the test application
- Try to provide a better default (e.g. `TIMER_DEV(1)` when
`ztimer_periph_timer` is in use, `TIMER_DEV(0)` otherwise)
The R-2R resistor ladder dac --> ADC test was disabled due to a bug in
the v0.1 version of the shield. Since this has been fixed in v0.2 and
v0.3 of the shield, it can be re-enabled.
The comment regarding the high accuracy of the resistor is dropped, as
v0.3 has been ordered with cost efficient resistors rather than with
accurate ones. As a result, the tolerance for error has been increased
to 10%. This quite a bit more lax than I have hoped for, but false
positives would be something to avoid.
- fix a copy-paste error (`TIMER_FREQ_UART_TEST` was used in the SPI
test, but that should be `TIMER_FREQ_SPI_TEST`)
- use 400 kHz as slow SPI frequency, as faster STM32 MCUs just cannot
divide the APB clock down to 100 kHz
- when detailed output is enabled, print the SPI clock in addition to
the SPI mode to ease figuring out what went wrong
- only have one `FAILURE` message for a too fast byte transfer per
check, rather than per transmitted byte, to reduce the noise
- work around a bug of `periph_timer` on STM32 by reducing the clock
speed of the timer for the SPI test
The test should execute only with `make test-with-config` and not with
`make test`, as boards without the shield cannot pass the test.
For some reason I accidentally added both variants, which makes no
sense. This drops the `make test` variant.
Finally, the `README.md` is updated to refer to `make test-with-config`
instead of `make test`.
This test application makes use of the RIOT Peripheral Selftest Shield,
which connects e.g. PWM to ADC or SPI MOSI to SPI MISO, UART TXD to RXD,
etc. This provides quick and fully automated self testing capabilities.
Please note that the simplicity and ease of use of the hardware comes
with a prices: There are whole classes of issues that cannot be detected
automatically. This test cannot replace other testing approaches
(such as manual testing or PHiLIP on the HiL), but only complement them.
20022: pkg/lwip: add support for slipdev r=benpicco a=benpicco
20025: tests/drivers/at: fix device table overflow r=benpicco a=krzysztof-cabaj
### Contribution description
This PR fix device table overflow in `tests/driver/at`, which could lead to device crash.
### Testing procedure
PR was tested on two nucleo boards with 2 and 3 UARTs (nucleo-l476rg and nucleo-l496zg).
Flash `tests/driver/at` with and without this PR.
Output with this PR:
```
> main(): This is RIOT! (Version: 2022.07-devel-5083-g2b9e8-tests-drivers-at)
AT command test app
> init 5 9600
Wrong UART device number - should by in range 0-2.
>
```
Output without this PR:
```
> main(): This is RIOT! (Version: 2022.07-devel-5083-g2b9e8)
AT command test app
> init 5 9600
8001afd
*** RIOT kernel panic:
FAILED ASSERTION.
*** halted.
Context before hardfault:
r0: 0x0000000a
r1: 0x00000000
. . .
```
### Issues/PRs references
None
Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Co-authored-by: krzysztof-cabaj <kcabaj@gmail.com>
- add `static` qualifiers where sensible
- drop `volatile` qualifier that was incorrectly used
- add a comment on use of shared memory for inter-thread communication
19990: sys/psa_crypto: allow repeated initialization r=benpicco a=mguetschow
### Contribution description
- simple unit test which calls `psa_crypto_init()` twice
- fix to no re-initialize key slots (which left them in a broken state)
### Testing procedure
- `make -C tests/sys/psa_crypto all test` succeeds
- `git checkout HEAD~1 && make -C tests/sys/psa_crypto all test` fails
Co-authored-by: Mikolai Gütschow <mikolai.guetschow@tu-dresden.de>
20011: tests/unittests: add a unit test for ztimer r=benpicco a=maribu
### Contribution description
This adds test coverage for removing ztimers with focus on ensuring that offsets are correctly updated on subsequent timers (e.g. not having timers fire too early).
### Testing procedure
Run the unit tests (will be done by the CI as well). Maybe also introduce a random bug in `ztimer_remove()` and check if this is indeed caught by the unit tests.
### Issues/PRs references
Prompted by https://github.com/RIOT-OS/RIOT/pull/18977#issuecomment-1764258356
Co-authored-by: Marian Buschsieweke <marian.buschsieweke@posteo.net>
This adds test coverage for removing ztimers with focus on ensuring that
offsets are correctly updated on subsequent timers (e.g. not having
timers fire too early).
19465: drivers/mtd: use XFA for pointers to defined MTDs r=benpicco a=gschorcht
### Contribution description
This PR provides the support to hold pointers to defined MTDs within a XFA. The XFA allows
- to access MTDs of different types (`mtd_flashpage`, `mtd_sdcard`, `mtd_emulated`, ...) by an index
- to determine the number of MTDs defined in the system.
### Testing procedure
To be defined once PR #19443 is merged because emulated MTDs will allow to test this PR on arbitrary boards.
### Porting Guide
For external boards:
- remove the `MTD_NUMOF` definition from `board.h`
- add `MTD_XFA_ADD(<mtd_dev>, <idx>);` to the definition of `<mtd_dev>`.
- `MTD_0`, `MTD_1`, … defines are no longer needed.
### Issues/PRs references
Related to PR #19443
19981: Fletcher32: Add incremental API r=benpicco a=bergzand
### Contribution description
This PR extends the current fletcher32 checksum with an incremental API mode. This way the bytes to be checksummed can be supplied via multiple successive calls and do not have to be provided in a single consecutive buffer.
I've also rephrased the warning with the original function a bit as that function uses an `unaligned_get_u16` to access the data. The data thus does not require alignment, but the length does need to be supplied as number of 16 bit words.
### Testing procedure
The test has been extended
### Issues/PRs references
None
19995: sys/psa_crypto: Fix macro for public key max size and SE example r=benpicco a=Einhornhool
### Contribution description
#### 1. Wrong public key size when using secure elements, introduced by #19954
Fixed conditions for key size macros in `crypto_sizes.h`.
#### 2. EdDSA and ECDSA examples fail when using a secure element because of unsopported changes introduced by #19954
Updated `example/psa_crypto` to use only supported functions for secure elements.
### Testing procedure
Build `example/psa_crypto` for secure elements and run application
Output on master:
```
2023-10-19 14:33:24,372 # main(): This is RIOT! (Version: 2019.07-devel-22378-gb6772)
2023-10-19 14:33:24,372 # HMAC SHA256 took 56393 us
2023-10-19 14:33:24,372 # Cipher AES 128 took 68826 us
2023-10-19 14:33:24,372 # *** RIOT kernel panic:
2023-10-19 14:33:24,373 # HARD FAULT HANDLER
2023-10-19 14:33:24,373 #
2023-10-19 14:33:24,373 # *** rebooting...
```
Output with fixes:
```
2023-10-19 13:35:24,715 # main(): This is RIOT! (Version: 2019.07-devel-22384-g8ef66-dev/psa-crypto-fixes)
2023-10-19 13:35:24,715 # HMAC SHA256 took 56374 us
2023-10-19 13:35:24,715 # Cipher AES 128 took 68805 us
2023-10-19 13:35:24,715 # ECDSA took 281164 us
2023-10-19 13:35:24,715 # All Done
```
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Koen Zandberg <koen@bergzand.net>
Co-authored-by: Lena Boeckmann <lena.boeckmann@haw-hamburg.de>
