In syscalls_init() there is a call to malloc(), which will return NULL if the heap is not initialized before, causing the entire board to fail booting if MODULE_ESP_IDF_HEAP is used.
19079: cpu/esp32: add periph_flashpage support r=kaspar030 a=gschorcht
### Contribution description
This PR provides the `periph_flashpage` support for ESP32x SoCs.
For byte-aligned read access to constant data in the flash, the MMU of all ESP32x SoCs allows to map a certain number of 64 kByte pages of the flash into the data address space of the CPU. This address space is called DROM. Normally the whole DROM address space is assigned to the section `.rodata`. The default flash layout used by all ESP32x SoCs is:
| Address in Flash | Content |
|:-----------------------|:-----------|
| `0x0000` or `0x1000` | bootloader |
| `0x8000` | parition table |
| `0x9000` | `nvs` parition with WiFi data |
| `0xf000` | `phy_init` partition with RF data |
| `0x10000` | `factory` partition with the app image |
The factory partition consists of a number of 64 kByte pages for the sections `.text`, `.rodata`, `.bss` and others. The `.text` and `rodata` sections are page-aligned and are simply mapped into the instruction address space (IROM) and the data address space (DROM), respectively. All other sections are loaded into RAM.
If the `periph_flashpage` module is used, the `periph_flashpage` driver
- decreases the size of the `.rodata` section in DROM address space by `CONFIG_ESP_FLASHPAGE_CAPACITY`,
- adds a section `.flashpage.writable` of size `CONFIG_ESP_FLASHPAGE_CAPACITY` at the end of DROM address space that is mapped into data address space of the CPU,
- reserves a region of size `CONFIG_ESP_FLASHPAGE_CAPACITY` starting from `0x10000` in front of the image partition `factory` and
- moves the image partition `factory` by `CONFIG_ESP_FLASHPAGE_CAPACITY` to address `0x10000 + CONFIG_ESP_FLASHPAGE_CAPACITY`.
The new flash layout is then:
| Address in Flash | Content |
|:-----------------------|:-----------|
| `0x0000` or `0x1000` | bootloader |
| `0x8000` | parition table |
| `0x9000` | `nvs` parition with WiFi data |
| `0xf000` | `phy_init` partition with RF data |
| `0x10000` | flashpage region |
| `0x10000 + CONFIG_ESP_FLASHPAGE_CAPACITY` | `factory` partition with the app image |
This guarantees that the flash pages are not overwritten if a new app image with changed size is flashed. `CONFIG_ESP_FLASHPAGE_CAPACITY` has to be a multiple of 64 kBytes.
~The PR includes PR #19077 and PR #19078 for the moment to be compilable.~
### Testing procedure
The following tests should pass.
```
USEMODULE='esp_log_startup ps shell_cmds_default' BOARD=esp32-wroom-32 make -j8 -C tests/periph_flashpage flash term
```
```
USEMODULE='esp_log_startup ps shell_cmds_default' BOARD=esp32-wroom-32 make -j8 -C tests/mtd_flashpage flash term
```
### Issues/PRs references
Depends on PR #19077
Depends on PR #19078
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Since PR #19100 it is possible to define:
- other pins for `UART_DEV(0)` than the default pins
- different `UART_DEV(0)` pins for the bootloader and RIOT
To allow correct reinitialization of the UART pins used by the bootloader as well as their usage for other purposes, the pin usage for the default UART0 pins and the UART pins used by the bootloader are reset to `_GPIO`. This is done in `uart_system_init` which has to be called earlier in the startup procedure.
If LOG_LEVEL >= 4, such as in `tests/log_printfnoformat`, the ESP-IDF config function called for the GPIO pins of the UART will output the configuration with `printf` before the `_GLOBAL_REENT` structure is initialized. This causes a crash during system startup. Therefore the initialization by `syscalls_init` must be called earlier in the startup procedure.
ESP32 has an esp_timer thread in addition to the main and the idle
thread. So applications that work fine with 2 threads on other
platforms will break on ESP32.
GPIO32 and GPIO33 are used during boot to start an 32.768 kHz XTAL if it is connected to these GPIOs. If the 32.768 kHz XTAL is not connected, these pins can be used digital IO. However, the 32.678 kHz XTAL has to be disabled explicitly in this case. Furthermore, the handling of GPIOs greater than GPIO31 had to be fixed in I2C software implementation.
The explicit call of rtc_init during the CPU start was removed because rtc_init is called within the function periph_init. The display of the system time at startup had to be placed after the call to periph_init.
Startup information, including board configuration, is only printed when module esp_log_startup is used. This reduces the amount of information that is printed by default to the console during the startup. The user can enable module esp_log_startup to get the additional startup information.
The UART peripheral clock seems to be sporadically set to wrong value when the CPU clock is changed. In this case, the UART clock is not set to 115.200 kbps but to 96 kbps, so that the output in the console seems like garbage. This can also cause automatic tests to fail. Therefore, the CPU clock is only changed if CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ defines a different default CPU clock than the one already used at boot time.
Module `newlib` is now used by default. Therefore, the separation of initialization of ctors and the newlibc is not needed any longer. Instead of calling `do_global_ctors` and `_init` separately, `__libc_init_array` is called. Explicit function `do_global_ctors` is removed.
Initializing the stdio file descriptors in global reent structure with newlib fake stdio file descriptors led to the problem that newlib stdio functions printf and puts were not working since they can't operate on these fake stdio file descriptors. Therefore, this initialization was removed. Now, the real stdio file descriptors as created automatically by newlib are used. Specific functions `printf`, `puts`, `getchar`and `putchar` are not required any longer and are removed now.
Modules newlib and newlib_syscalls_default are now used by default. Conditional compilations for MODULE_NEWLIB_SYSCALLS_DEFAULT as well as alternative code are removed completely.
Some ESP32 boards (like my SparkFun ESP32 Thing) have a main clock
crystal that runs at 26MHz, not 40MHz. RIOT appears to assume 40MHz.
The mismatch causes the UART to not sync properly, resulting in
garbage written to the terminal instead of log output.
I’ve added:
* A new board configuration constant ESP32_XTAL_FREQ that defaults
to 40, but can be overridden by a board def or at build time to
force a specific value (i.e. 26).
* Some code spliced into system_clk_init() to check this constant and
call rtc_clk_init() to set the correct frequency.
* A copy of the rtf_clk_init() function from the ESP-IDF sources.
Fixes#10272
Xtensa newlib version requires pthread_setcancelstate as symbol. Therefore, the module pthread was always used, which in turn requires the module xtimer. The xtimer module, however, uses TIMER_DEV(0). Therefore, tests/timers failed for TIMER_DEV(0).
