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cpu/esp32: fix compilation with gcc 12.2

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This commit is contained in:
Gunar Schorcht 2023-04-05 13:47:34 +02:00
parent 3d1f3fea46
commit 0de2570802
14 changed files with 97 additions and 34 deletions
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13
cpu/esp32/Makefile.include
View File

@ -207,6 +207,13 @@ CFLAGS += -D_CONST=const
# TODO no relaxation yet
ifneq (,$(filter riscv%,$(TARGET_ARCH)))
CFLAGS += -mno-relax -march=rv32imc -mabi=ilp32 -DRISCV_NO_RELAX
GCC_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | \
$(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 \
-misa-spec=2.2 -E - > /dev/null 2>&1 && \
echo 1 || echo 0)
ifeq (1,$(GCC_NEW_RISCV_ISA))
CFLAGS += -misa-spec=2.2
endif
endif
ifneq (,$(filter xtensa%,$(TARGET_ARCH)))
@ -243,6 +250,12 @@ endif
LINKFLAGS += -nostdlib -lgcc -Wl,-gc-sections
# all ESP32x SoCs have to load executable code into IRAM
# warning 'LOAD segment with RWX permissions' has to be disabled therefore
ifeq (1,$(GCC_NEW_RISCV_ISA))
LINKFLAGS += -Wl,--no-warn-rwx-segments
endif
# Libraries needed when using esp_wifi_any pseudomodule
ifneq (,$(filter esp_wifi_any,$(USEMODULE)))
LINKFLAGS += -L$(ESP32_SDK_LIB_WIFI_DIR)/$(CPU_FAM)

7
cpu/esp32/bootloader/Makefile
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@ -171,6 +171,13 @@ ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
CFLAGS += -Wno-error=format=
CFLAGS += -nostartfiles
CFLAGS += -Wno-format
GCC_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | \
$(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 \
-misa-spec=2.2 -E - > /dev/null 2>&1 && \
echo 1 || echo 0)
ifeq (1,$(GCC_NEW_RISCV_ISA))
CFLAGS += -misa-spec=2.2
endif
endif
ifneq (,$(filter xtensa%,$(TARGET_ARCH)))

7
cpu/esp32/esp-idf/esp_idf_cflags.mk
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@ -42,4 +42,11 @@ ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
CFLAGS += -Wno-error=format=
CFLAGS += -nostartfiles
CFLAGS += -Wno-format
GCC_NEW_RISCV_ISA ?= $(shell echo "typedef int dont_be_pedantic;" | \
$(TARGET_ARCH)-gcc -march=rv32imac -mabi=ilp32 \
-misa-spec=2.2 -E - > /dev/null 2>&1 && \
echo 1 || echo 0)
ifeq (1,$(GCC_NEW_RISCV_ISA))
CFLAGS += -misa-spec=2.2
endif
endif

2
cpu/esp32/esp-idf/esp_idf_support.c
View File

@ -111,7 +111,7 @@ void IRAM_ATTR esp_log_writev(esp_log_level_t level,
* We use the log level set for the given tag instead of using
* the given log level.
*/
esp_log_level_t act_level = LOG_DEBUG;
esp_log_level_t act_level = (esp_log_level_t)LOG_DEBUG;
size_t i;
for (i = 0; i < ARRAY_SIZE(_log_levels); i++) {
if (strcmp(tag, _log_levels[i].tag) == 0) {

10
cpu/esp32/include/periph_cpu.h
View File

@ -212,16 +212,6 @@ typedef enum {
#define GPIO_DRIVE_20 GPIO_DRIVE_STRONG /**< 20 mA (default) */
#define GPIO_DRIVE_30 GPIO_DRIVE_STRONGEST /**< 30 mA */
#define HAVE_GPIO_IRQ_TRIG_T
typedef enum {
GPIO_TRIGGER_NONE = 0,
GPIO_TRIGGER_EDGE_RISING = 1,
GPIO_TRIGGER_EDGE_FALLING = 2,
GPIO_TRIGGER_EDGE_BOTH = 3,
GPIO_TRIGGER_LEVEL_LOW = 4,
GPIO_TRIGGER_LEVEL_HIGH = 5
} gpio_irq_trig_t;
/* END: GPIO LL overwrites */
#endif /* ndef DOXYGEN */

26
cpu/esp32/periph/adc.c
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@ -131,16 +131,22 @@ int adc_init(adc_t line)
}
if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_1) {
/* ensure compatibility of given adc_channel_t with adc1_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC1_CHANNEL_MAX);
/* initialize the ADC1 unit if needed */
_adc1_ctrl_init();
/* set the attenuation and configure its associated GPIO pin mux */
adc1_config_channel_atten(_adc_hw[rtcio].adc_channel, ADC_ATTEN_DB_11);
adc1_config_channel_atten((adc1_channel_t)_adc_hw[rtcio].adc_channel,
ADC_ATTEN_DB_11);
}
else if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_2) {
/* ensure compatibility of given adc_channel_t with adc2_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC2_CHANNEL_MAX);
/* initialize the ADC2 unit if needed */
_adc2_ctrl_init();
/* set the attenuation and configure its associated GPIO pin mux */
adc2_config_channel_atten(_adc_hw[rtcio].adc_channel, ADC_ATTEN_DB_11);
adc2_config_channel_atten((adc2_channel_t)_adc_hw[rtcio].adc_channel,
ADC_ATTEN_DB_11);
}
else {
return -1;
@ -165,13 +171,17 @@ int32_t adc_sample(adc_t line, adc_res_t res)
if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_1) {
adc1_config_width(_adc_esp_res_map[res].res);
raw = adc1_get_raw(_adc_hw[rtcio].adc_channel);
/* ensure compatibility of given adc_channel_t with adc1_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC1_CHANNEL_MAX);
raw = adc1_get_raw((adc1_channel_t)_adc_hw[rtcio].adc_channel);
if (raw < 0) {
return -1;
}
}
else if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_2) {
if (adc2_get_raw(_adc_hw[rtcio].adc_channel,
/* ensure compatibility of given adc_channel_t with adc2_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC2_CHANNEL_MAX);
if (adc2_get_raw((adc2_channel_t)_adc_hw[rtcio].adc_channel,
_adc_esp_res_map[res].res, &raw) < 0) {
return -1;
}
@ -189,10 +199,14 @@ int adc_set_attenuation(adc_t line, adc_atten_t atten)
assert(rtcio != RTCIO_NA);
if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_1) {
return adc1_config_channel_atten(_adc_hw[rtcio].adc_channel, atten);
/* ensure compatibility of given adc_channel_t with adc1_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC1_CHANNEL_MAX);
return adc1_config_channel_atten((adc1_channel_t)_adc_hw[rtcio].adc_channel, atten);
}
else if (_adc_hw[rtcio].adc_ctrl == ADC_UNIT_2) {
return adc2_config_channel_atten(_adc_hw[rtcio].adc_channel, atten);
/* ensure compatibility of given adc_channel_t with adc2_channel_t */
assert(_adc_hw[rtcio].adc_channel < (adc_channel_t)ADC2_CHANNEL_MAX);
return adc2_config_channel_atten((adc2_channel_t)_adc_hw[rtcio].adc_channel, atten);
}
return -1;

4
cpu/esp32/periph/flashpage.c
View File

@ -76,8 +76,8 @@ void IRAM_ATTR esp_flashpage_init(void)
p_addr, 64, p_numof, 0);
Cache_Resume_ICache(autoload);
DEBUG("%s DCache MMU set paddr=%08x vaddr=%08x size=%d n=%u\n", __func__,
p_addr, (uint32_t)&_fp_mem_start, CONFIG_ESP_FLASHPAGE_CAPACITY,
DEBUG("%s DCache MMU set paddr=%08"PRIx32" vaddr=%08"PRIx32" size=%d n=%"PRIu32"\n",
__func__, p_addr, (uint32_t)&_fp_mem_start, CONFIG_ESP_FLASHPAGE_CAPACITY,
p_numof);
if (res != ESP_OK) {

4
cpu/esp32/periph/gpio.c
View File

@ -229,8 +229,8 @@ int gpio_init(gpio_t pin, gpio_mode_t mode)
(mode == GPIO_OD_PU) ||
(mode == GPIO_IN_OD_PU)) ? GPIO_PULLUP_ENABLE
: GPIO_PULLUP_DISABLE;
cfg.pull_down_en = (mode == GPIO_IN_PD) ? GPIO_PULLUP_ENABLE
: GPIO_PULLUP_DISABLE;
cfg.pull_down_en = (mode == GPIO_IN_PD) ? GPIO_PULLDOWN_ENABLE
: GPIO_PULLDOWN_DISABLE;
cfg.intr_type = GPIO_INTR_DISABLE;
#ifdef ESP_PM_WUP_PINS

20
cpu/esp32/periph/gpio_ll.c
View File

@ -149,9 +149,25 @@ int gpio_ll_init(gpio_port_t port, uint8_t pin, const gpio_conf_t *conf)
}
/* if output pin, try to set drive strength */
gpio_drive_cap_t strength;
switch (conf->drive_strength) {
case GPIO_DRIVE_WEAKEST:
strength = GPIO_DRIVE_CAP_0;
break;
case GPIO_DRIVE_WEAK:
strength = GPIO_DRIVE_CAP_1;
break;
case GPIO_DRIVE_STRONG:
strength = GPIO_DRIVE_CAP_2;
break;
case GPIO_DRIVE_STRONGEST:
strength = GPIO_DRIVE_CAP_3;
break;
default:
strength = GPIO_DRIVE_CAP_DEFAULT;
}
if ((cfg.pin_bit_mask & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) &&
(esp_idf_gpio_set_drive_capability(gpio,
conf->drive_strength) != ESP_OK)) {
(esp_idf_gpio_set_drive_capability(gpio, strength) != ESP_OK)) {
return -ENOTSUP;
}

22
cpu/esp32/periph/gpio_ll_irq.c
View File

@ -75,7 +75,27 @@ int gpio_ll_irq(gpio_port_t port, uint8_t pin, gpio_irq_trig_t trig,
gpio_isr_service_installed = true;
/* set the interrupt type for the pin */
if (esp_idf_gpio_set_intr_type(gpio, trig) != ESP_OK) {
gpio_int_type_t type;
switch (trig) {
case GPIO_TRIGGER_EDGE_FALLING:
type = GPIO_INTR_NEGEDGE;
break;
case GPIO_TRIGGER_EDGE_RISING:
type = GPIO_INTR_POSEDGE;
break;
case GPIO_TRIGGER_EDGE_BOTH:
type = GPIO_INTR_ANYEDGE;
break;
case GPIO_TRIGGER_LEVEL_HIGH:
type = GPIO_INTR_HIGH_LEVEL;
break;
case GPIO_TRIGGER_LEVEL_LOW:
type = GPIO_INTR_LOW_LEVEL;
break;
default:
type = GPIO_INTR_DISABLE;
}
if (esp_idf_gpio_set_intr_type(gpio, type) != ESP_OK) {
return -1;
}

2
cpu/esp32/periph/rtt.c
View File

@ -58,7 +58,7 @@ extern uint32_t rtc_clk_slow_freq_get_hz(void);
/* forward declaration of functions */
void rtt_restore_counter(bool sys_time);
static void _rtt_update_hw_alarm(void);
static void IRAM_ATTR _rtt_isr(void *arg);
static void _rtt_isr(void *arg);
/* forward declarations of driver functions */
uint64_t _rtc_get_counter(void);

5
cpu/esp32/periph/rtt_hw_rtc.c
View File

@ -135,13 +135,8 @@ static void _rtc_set_alarm(uint32_t alarm, rtt_cb_t cb, void *arg)
RTCCNTL.slp_timer0 = rtc_alarm & 0xffffffff;
RTCCNTL.slp_timer1.slp_val_hi = rtc_alarm >> 32;
#if __xtensa__
DEBUG("%s %08x%08x \n", __func__,
RTCCNTL.slp_timer1.slp_val_hi, RTCCNTL.slp_timer0);
#else
DEBUG("%s %08x%08x \n", __func__,
(unsigned)RTCCNTL.slp_timer1.slp_val_hi, (unsigned)RTCCNTL.slp_timer0);
#endif
/* enable RTC timer alarm */
RTCCNTL.slp_timer1.main_timer_alarm_en = 1;

4
cpu/esp32/startup.c
View File

@ -240,8 +240,8 @@ static NORETURN void IRAM system_init (void)
/* set log levels for SDK library outputs */
extern void esp_log_level_set(const char* tag, esp_log_level_t level);
esp_log_level_set("wifi", LOG_DEBUG);
esp_log_level_set("gpio", LOG_DEBUG);
esp_log_level_set("wifi", (esp_log_level_t)LOG_DEBUG);
esp_log_level_set("gpio", (esp_log_level_t)LOG_DEBUG);
/* init watchdogs */
system_wdt_init();

5
cpu/esp32/syscalls.c
View File

@ -382,8 +382,9 @@ void system_wdt_init(void)
wdt_hal_write_protect_enable(&rwdt);
#if defined(CPU_FAM_ESP32)
DEBUG("%s TIMERG0 wdtconfig0=%08x wdtconfig1=%08x wdtconfig2=%08x "
"wdtconfig3=%08x wdtconfig4=%08x regclk=%08x\n", __func__,
DEBUG("%s TIMERG0 wdtconfig0=%08"PRIx32" wdtconfig1=%08"PRIx32
" wdtconfig2=%08"PRIx32" wdtconfig3=%08"PRIx32
" wdtconfig4=%08"PRIx32" regclk=%08"PRIx32"\n", __func__,
TIMERG0.wdt_config0.val, TIMERG0.wdt_config1.val,
TIMERG0.wdt_config2, TIMERG0.wdt_config3,
TIMERG0.wdt_config4, TIMERG0.clk.val);