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Merge #19079
19079: cpu/esp32: add periph_flashpage support r=kaspar030 a=gschorcht ### Contribution description This PR provides the `periph_flashpage` support for ESP32x SoCs. For byte-aligned read access to constant data in the flash, the MMU of all ESP32x SoCs allows to map a certain number of 64 kByte pages of the flash into the data address space of the CPU. This address space is called DROM. Normally the whole DROM address space is assigned to the section `.rodata`. The default flash layout used by all ESP32x SoCs is: | Address in Flash | Content | |:-----------------------|:-----------| | `0x0000` or `0x1000` | bootloader | | `0x8000` | parition table | | `0x9000` | `nvs` parition with WiFi data | | `0xf000` | `phy_init` partition with RF data | | `0x10000` | `factory` partition with the app image | The factory partition consists of a number of 64 kByte pages for the sections `.text`, `.rodata`, `.bss` and others. The `.text` and `rodata` sections are page-aligned and are simply mapped into the instruction address space (IROM) and the data address space (DROM), respectively. All other sections are loaded into RAM. If the `periph_flashpage` module is used, the `periph_flashpage` driver - decreases the size of the `.rodata` section in DROM address space by `CONFIG_ESP_FLASHPAGE_CAPACITY`, - adds a section `.flashpage.writable` of size `CONFIG_ESP_FLASHPAGE_CAPACITY` at the end of DROM address space that is mapped into data address space of the CPU, - reserves a region of size `CONFIG_ESP_FLASHPAGE_CAPACITY` starting from `0x10000` in front of the image partition `factory` and - moves the image partition `factory` by `CONFIG_ESP_FLASHPAGE_CAPACITY` to address `0x10000 + CONFIG_ESP_FLASHPAGE_CAPACITY`. The new flash layout is then: | Address in Flash | Content | |:-----------------------|:-----------| | `0x0000` or `0x1000` | bootloader | | `0x8000` | parition table | | `0x9000` | `nvs` parition with WiFi data | | `0xf000` | `phy_init` partition with RF data | | `0x10000` | flashpage region | | `0x10000 + CONFIG_ESP_FLASHPAGE_CAPACITY` | `factory` partition with the app image | This guarantees that the flash pages are not overwritten if a new app image with changed size is flashed. `CONFIG_ESP_FLASHPAGE_CAPACITY` has to be a multiple of 64 kBytes. ~The PR includes PR #19077 and PR #19078 for the moment to be compilable.~ ### Testing procedure The following tests should pass. ``` USEMODULE='esp_log_startup ps shell_cmds_default' BOARD=esp32-wroom-32 make -j8 -C tests/periph_flashpage flash term ``` ``` USEMODULE='esp_log_startup ps shell_cmds_default' BOARD=esp32-wroom-32 make -j8 -C tests/mtd_flashpage flash term ``` ### Issues/PRs references Depends on PR #19077 Depends on PR #19078 Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
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7855aad7e4
@ -17,6 +17,9 @@ config CPU_FAM_ESP32
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select HAS_ESP_BLE_ESP32
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select HAS_ESP_HW_COUNTER
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select HAS_ESP_WIFI_ENTERPRISE
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select HAS_PERIPH_FLASHPAGE
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select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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select HAS_PERIPH_GPIO_LL
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select HAS_PERIPH_GPIO_LL_IRQ
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
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@ -18,6 +18,9 @@ config CPU_FAM_ESP32C3
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select HAS_ESP_BLE
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select HAS_ESP_BLE_ESP32C3
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select HAS_ESP_WIFI_ENTERPRISE
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select HAS_PERIPH_FLASHPAGE
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select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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select HAS_PERIPH_GPIO_LL
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select HAS_PERIPH_GPIO_LL_IRQ
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
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@ -13,6 +13,9 @@ config CPU_FAM_ESP32S2
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select HAS_CPU_ESP32
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select HAS_ESP_HW_COUNTER
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select HAS_ESP_WIFI_ENTERPRISE
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select HAS_PERIPH_FLASHPAGE
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select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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select HAS_PERIPH_GPIO_LL
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select HAS_PERIPH_GPIO_LL_IRQ
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
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@ -19,6 +19,9 @@ config CPU_FAM_ESP32S3
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select HAS_ESP_BLE_ESP32C3
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select HAS_ESP_HW_COUNTER
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select HAS_ESP_WIFI_ENTERPRISE
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select HAS_PERIPH_FLASHPAGE
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select HAS_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE
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select HAS_PERIPH_FLASHPAGE_PAGEWISE
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select HAS_PERIPH_GPIO_LL
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select HAS_PERIPH_GPIO_LL_IRQ
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select HAS_PERIPH_GPIO_LL_IRQ_LEVEL_TRIGGERED_HIGH
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@ -128,7 +128,7 @@ ifneq (,$(filter esp_idf_heap,$(USEMODULE)))
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USEPKG += tlsf
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endif
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ifneq (,$(filter mtd,$(USEMODULE)))
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ifneq (,$(filter mtd periph_flashpage,$(USEMODULE)))
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USEMODULE += esp_idf_spi_flash
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endif
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@ -17,6 +17,9 @@ include $(RIOTCPU)/esp_common/Makefile.features
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FEATURES_PROVIDED += arch_esp32
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FEATURES_PROVIDED += esp_wifi_enterprise
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FEATURES_PROVIDED += periph_flashpage
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FEATURES_PROVIDED += periph_flashpage_in_address_space
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FEATURES_PROVIDED += periph_flashpage_pagewise
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FEATURES_PROVIDED += periph_gpio_ll
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FEATURES_PROVIDED += periph_gpio_ll_irq
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FEATURES_PROVIDED += periph_gpio_ll_irq_level_triggered_high
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@ -23,6 +23,38 @@ else ifneq (,$(filter esp32s2,$(CPU_FAM)))
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else
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$(error Unkwnown ESP32x SoC variant (family))
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endif
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ifneq (,$(filter periph_flashpage,$(USEMODULE)))
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ifneq (,$(CONFIG_ESP_FLASHPAGE_CAPACITY_64K))
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FLASHFILE_POS = 0x20000
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FLASHPAGE_CAP = 0x10000
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else ifneq (,$(CONFIG_ESP_FLASHPAGE_CAPACITY_128K))
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FLASHFILE_POS = 0x30000
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FLASHPAGE_CAP = 0x20000
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else ifneq (,$(CONFIG_ESP_FLASHPAGE_CAPACITY_256K))
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FLASHFILE_POS = 0x50000
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FLASHPAGE_CAP = 0x40000
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else ifneq (,$(CONFIG_ESP_FLASHPAGE_CAPACITY_512K))
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FLASHFILE_POS = 0x90000
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FLASHPAGE_CAP = 0x80000
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else ifneq (,$(CONFIG_ESP_FLASHPAGE_CAPACITY_1M))
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FLASHFILE_POS = 0x110000
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FLASHPAGE_CAP = 0x100000
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else ifneq (,$(CONFIG_ESP_FLASHPAGE_CAPACITY_2M))
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FLASHFILE_POS = 0x210000
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FLASHPAGE_CAP = 0x200000
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else
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# use 512 kByte for periph_flashpage by default
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FLASHFILE_POS = 0x90000
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FLASHPAGE_CAP = 0x80000
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CFLAGS += -DCONFIG_ESP_FLASHPAGE_CAPACITY_512K
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endif
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FLASHPAGE_ADDR_START = 0x10000
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FLASHPAGE_ADDR_END = $(FLASHFILE_POS)
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CFLAGS += -DFLASHPAGE_ADDR_START=$(FLASHPAGE_ADDR_START)
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CFLAGS += -DFLASHPAGE_ADDR_END=$(FLASHPAGE_ADDR_END)
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endif
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FLASHFILE_POS ?= 0x10000
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ESPTOOL ?= $(RIOTTOOLS)/esptools/esptool_v3.2.py
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@ -76,6 +108,7 @@ INCLUDES += -I$(ESP32_SDK_DIR)/components/log/include
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INCLUDES += -I$(ESP32_SDK_DIR)/components/newlib/platform_include
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INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/include
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INCLUDES += -I$(ESP32_SDK_DIR)/components/soc/$(CPU_FAM)/include
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INCLUDES += -I$(ESP32_SDK_DIR)/components/spi_flash/include
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ifneq (,$(filter riscv32%,$(TARGET_ARCH)))
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INCLUDES += -I$(ESP32_SDK_DIR)/components/riscv/include
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@ -13,7 +13,7 @@ config MODULE_ESP_IDF
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default y
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select MODULE_ESP_IDF_COMMON
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select MODULE_ESP_IDF_EFUSE
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select MODULE_ESP_IDF_SPI_FLASH if MODULE_MTD
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select MODULE_ESP_IDF_SPI_FLASH if MODULE_MTD || MODULE_PERIPH_FLASHPAGE
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select MODULE_ESP_IDF_USB if MODULE_TINYUSB_PORTABLE_ESPRESSIF
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help
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Espressif IoT Development Framework.
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@ -22,6 +22,10 @@
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#ifndef CPU_CONF_H
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#define CPU_CONF_H
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#if !defined(__ASSEMBLER__)
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#include <stdint.h>
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#endif
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/**
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* @name Stack size configuration
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* @{
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@ -60,6 +64,41 @@
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*/
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#define PUF_SRAM_ATTRIBUTES __attribute__((used, section(".noinit")))
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/**
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* @brief Support of unaligned access
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*
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* All ESP32x SoCs allow unaligned read/write access to the RAM as well as
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* unaligned read access to the constant data in the flash, which is accessible
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* via the data bus and mapped by the MMU into the data address space of
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* the CPU.
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*/
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#define CPU_HAS_UNALIGNED_ACCESS 1
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/**
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* @name Flash page configuration
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* @{
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*/
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#if !DOXYGEN && !defined(__ASSEMBLER__)
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/* start address of flash pages in CPU address space as determined by the linker */
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extern uint8_t _fp_mem_start;
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#endif
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#define FLASHPAGE_SIZE (4096U) /**< Size of pages (flash sectors) in bytes */
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#define FLASHPAGE_WRITE_BLOCK_SIZE (4U) /**< Minimum write block size */
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#define FLASHPAGE_WRITE_BLOCK_ALIGNMENT (4U) /**< Write block alignment */
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/**
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* @brief Number of pages
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*/
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#define FLASHPAGE_NUMOF (CONFIG_ESP_FLASHPAGE_CAPACITY / FLASHPAGE_SIZE)
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/**
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* @brief CPU base address for flash page access as determined by the linker
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*/
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#define CPU_FLASH_BASE ((uint32_t)&_fp_mem_start)
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/** @} */
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/* include ESP32x SoC specific compile time configurations */
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#if defined(CPU_FAM_ESP32)
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#include "cpu_conf_esp32.h"
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@ -206,6 +206,33 @@
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#define CONFIG_ESP32_PHY_CALIBRATION_AND_DATA_STORAGE CONFIG_ESP_PHY_CALIBRATION_AND_DATA_STORAGE
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#define CONFIG_ESP32_PHY_MAX_WIFI_TX_POWER CONFIG_ESP_PHY_MAX_WIFI_TX_POWER
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/**
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* Flashpage configuration
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*/
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#ifndef CONFIG_ESP_FLASHPAGE_CAPACITY
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#ifdef MODULE_PERIPH_FLASHPAGE
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#if CONFIG_ESP_FLASHPAGE_CAPACITY_64K
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x10000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_128K
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x20000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_256K
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x40000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_512K
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_1M
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x100000
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#elif CONFIG_ESP_FLASHPAGE_CAPACITY_2M
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x200000
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#else
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x80000
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#endif
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#else /* MODULE_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE */
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#define CONFIG_ESP_FLASHPAGE_CAPACITY 0x0
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#endif /* MODULE_PERIPH_FLASHPAGE_IN_ADDRESS_SPACE */
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#endif /* !CONFIG_ESP_FLASHPAGE_CAPACITY */
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#endif /* DOXYGEN */
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/**
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@ -84,9 +84,16 @@ MEMORY
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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#ifdef MODULE_PERIPH_FLASHPAGE
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drom0_0_seg (R) : org = 0x3F400020,
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len = 0x400000 - 0x20 - CONFIG_ESP_FLASHPAGE_CAPACITY
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drom0_1_seg (R) : org = ORIGIN(drom0_0_seg) + LENGTH(drom0_0_seg),
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len = CONFIG_ESP_FLASHPAGE_CAPACITY
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#else
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drom0_0_seg (R) : org = 0x3F400020, len = 0x400000-0x20
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/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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#endif /* MODULE_PERIPH_FLASHPAGE */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* RTC fast memory (executable). Persists over deep sleep.
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@ -466,7 +466,6 @@ SECTIONS
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. = ALIGN(ALIGNOF(.flash.rodata));
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} >default_rodata_seg
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_rodata_start = ABSOLUTE(.);
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.flash.rodata : ALIGN(0x10)
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{
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_flash_rodata_start = ABSOLUTE(.);
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@ -617,6 +616,17 @@ SECTIONS
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_heap_start = ABSOLUTE(.);
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_sheap = ABSOLUTE(.);
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} > dram0_0_seg
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#ifdef MODULE_PERIPH_FLASHPAGE
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.flash_writable (NOLOAD) : ALIGN(65536)
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{
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_fp_mem_start = . ;
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KEEP(*(SORT(.flash_writable.*)))
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_fp_mem_end = . ;
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. = ALIGN(4096);
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_end_fw = . ;
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} > drom0_1_seg
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#endif
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}
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ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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@ -72,9 +72,16 @@ MEMORY
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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#ifdef MODULE_PERIPH_FLASHPAGE
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drom0_0_seg (R) : org = 0x3C000020,
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len = 0x800000 - 0x20 - CONFIG_ESP_FLASHPAGE_CAPACITY
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drom0_1_seg (R) : org = ORIGIN(drom0_0_seg) + LENGTH(drom0_0_seg),
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len = CONFIG_ESP_FLASHPAGE_CAPACITY
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#else
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drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
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/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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#endif /* MODULE_PERIPH_FLASHPAGE */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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@ -599,6 +599,16 @@ SECTIONS
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} > dram0_0_seg
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_eheap = phy_param_rom;
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#ifdef MODULE_PERIPH_FLASHPAGE
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.flash_writable (NOLOAD) : ALIGN(65536)
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{
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_fp_mem_start = . ;
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KEEP(*(SORT(.flash_writable.*)))
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_fp_mem_end = . ;
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. = ALIGN(4096);
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_end_fw = . ;
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} > drom0_1_seg
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#endif
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}
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ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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@ -90,9 +90,16 @@ MEMORY
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#ifdef CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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#ifdef MODULE_PERIPH_FLASHPAGE
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drom0_0_seg (R) : org = 0x3F000020,
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len = 0x3f0000-0x20 - CONFIG_ESP_FLASHPAGE_CAPACITY
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drom0_1_seg (R) : org = ORIGIN(drom0_0_seg) + LENGTH(drom0_0_seg),
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len = CONFIG_ESP_FLASHPAGE_CAPACITY
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#else
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drom0_0_seg (R) : org = 0x3F000020, len = 0x3f0000-0x20
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/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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#endif /* MODULE_PERIPH_FLASHPAGE */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* RTC fast memory (executable). Persists over deep sleep.
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@ -592,6 +592,17 @@ SECTIONS
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. = _heap_end;
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_eheap = ABSOLUTE(.);
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#ifdef MODULE_PERIPH_FLASHPAGE
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.flash_writable (NOLOAD) : ALIGN(65536)
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{
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_fp_mem_start = . ;
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KEEP(*(SORT(.flash_writable.*)))
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_fp_mem_end = . ;
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. = ALIGN(4096);
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_end_fw = . ;
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} > drom0_1_seg
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#endif
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}
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ASSERT(((_iram_text_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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@ -90,9 +90,16 @@ MEMORY
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#if CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/* Flash mapped constant data */
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#ifdef MODULE_PERIPH_FLASHPAGE
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drom0_0_seg (R) : org = 0x3C000020,
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len = 0x800000-0x20 - CONFIG_ESP_FLASHPAGE_CAPACITY
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drom0_1_seg (R) : org = ORIGIN(drom0_0_seg) + LENGTH(drom0_0_seg),
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len = CONFIG_ESP_FLASHPAGE_CAPACITY
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#else
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drom0_0_seg (R) : org = 0x3C000020, len = 0x800000-0x20
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/* (See iram0_2_seg for meaning of 0x20 offset in the above.) */
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#endif /* MODULE_PERIPH_FLASHPAGE */
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#endif // CONFIG_APP_BUILD_USE_FLASH_SECTIONS
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/**
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@ -619,6 +619,17 @@ SECTIONS
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. = _heap_end;
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_eheap = ABSOLUTE(.);
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#ifdef MODULE_PERIPH_FLASHPAGE
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.flash_writable (NOLOAD) : ALIGN(65536)
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{
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_fp_mem_start = . ;
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KEEP(*(SORT(.flash_writable.*)))
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_fp_mem_end = . ;
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. = ALIGN(4096);
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_end_fw = . ;
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} > drom0_1_seg
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#endif
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}
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ASSERT(((_iram_end - ORIGIN(iram0_0_seg)) <= LENGTH(iram0_0_seg)),
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@ -31,4 +31,22 @@ config MODULE_ESP_HW_COUNTER
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registers that can be used as low-level timer peripherals. Use this
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option to enable these CCOUNT and CCOMPARE register as low-level timer.
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choice ESP_FLASHPAGE_CAPACITY
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bool "Flashpage capacity"
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default ESP_FLASHPAGE_CAPACITY_512K
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depends on MODULE_PERIPH_FLASHPAGE
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config ESP_FLASHPAGE_CAPACITY_64K
|
||||
bool "64 kByte"
|
||||
config ESP_FLASHPAGE_CAPACITY_128K
|
||||
bool "128 kByte"
|
||||
config ESP_FLASHPAGE_CAPACITY_256K
|
||||
bool "256 kByte"
|
||||
config ESP_FLASHPAGE_CAPACITY_512K
|
||||
bool "512 kByte"
|
||||
config ESP_FLASHPAGE_CAPACITY_1M
|
||||
bool "1 MByte"
|
||||
config ESP_FLASHPAGE_CAPACITY_2M
|
||||
bool "2 MByte"
|
||||
endchoice
|
||||
|
||||
endif # TEST_KCONFIG
|
||||
|
||||
161
cpu/esp32/periph/flashpage.c
Normal file
161
cpu/esp32/periph/flashpage.c
Normal file
@ -0,0 +1,161 @@
|
||||
/*
|
||||
* Copyright (C) 2022 Gunar Schorcht
|
||||
*
|
||||
* This file is subject to the terms and conditions of the GNU Lesser
|
||||
* General Public License v2.1. See the file LICENSE in the top level
|
||||
* directory for more details.
|
||||
*/
|
||||
|
||||
/**
|
||||
* @ingroup cpu_esp32
|
||||
* @{
|
||||
*
|
||||
* @file
|
||||
* @brief Implementation of the peripheral flashpage interface
|
||||
*
|
||||
* @author Gunar Schorcht <gunar@schorcht.net>
|
||||
* @}
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
|
||||
#include "architecture.h"
|
||||
#include "cpu.h"
|
||||
#include "irq.h"
|
||||
#include "periph/flashpage.h"
|
||||
|
||||
#include "irq.h"
|
||||
#include "log.h"
|
||||
|
||||
#include "esp_flash_partitions.h"
|
||||
#include "esp_spi_flash.h"
|
||||
#include "rom/cache.h"
|
||||
#include "rom/spi_flash.h"
|
||||
#include "soc/mmu.h"
|
||||
#include "soc/soc.h"
|
||||
|
||||
#define ENABLE_DEBUG 0
|
||||
#include "debug.h"
|
||||
|
||||
#define ESP_PART_TABLE_ADDR 0x8000 /* TODO configurable as used in Makefile.include */
|
||||
#define ESP_PART_TABLE_SIZE 0xC00
|
||||
#define ESP_PART_ENTRY_SIZE 0x20
|
||||
#define ESP_PART_ENTRY_MAGIC ESP_PARTITION_MAGIC
|
||||
|
||||
extern uint8_t _fp_mem_start; /* start address in CPU address space */
|
||||
extern uint8_t _fp_mem_end;
|
||||
extern uint8_t _end_fw;
|
||||
|
||||
static uint32_t _fp_flash_start; /* start address in flash */
|
||||
|
||||
void IRAM_ATTR esp_flashpage_init(void)
|
||||
{
|
||||
/* CONFIG_ESP_FLASHPAGE_CAPACITY has to be a multiple of SPI_FLASH_MMU_PAGE_SIZE */
|
||||
assert((CONFIG_ESP_FLASHPAGE_CAPACITY % SPI_FLASH_MMU_PAGE_SIZE) == 0);
|
||||
|
||||
DEBUG("%s pages in CPU address space @0x%08"PRIx32"...0x%08"PRIx32"\n", __func__,
|
||||
CPU_FLASH_BASE, CPU_FLASH_BASE + CONFIG_ESP_FLASHPAGE_CAPACITY - 1);
|
||||
|
||||
_fp_flash_start = FLASHPAGE_ADDR_START;
|
||||
|
||||
DEBUG("%s pages in flash @0x%08"PRIx32"...0x%08"PRIx32"\n", __func__,
|
||||
_fp_flash_start, _fp_flash_start + CONFIG_ESP_FLASHPAGE_CAPACITY - 1);
|
||||
|
||||
uint32_t state = irq_disable();
|
||||
|
||||
uint32_t p_numof = CONFIG_ESP_FLASHPAGE_CAPACITY / SPI_FLASH_MMU_PAGE_SIZE;
|
||||
uint32_t p_addr = FLASHPAGE_ADDR_START;
|
||||
|
||||
#if CPU_FAM_ESP32S2
|
||||
/* ESP32-S2 requires special handling to enable the MMU pages in Cache
|
||||
* explicitly */
|
||||
|
||||
uint32_t autoload = Cache_Suspend_ICache();
|
||||
Cache_Invalidate_ICache_All();
|
||||
int res = Cache_Ibus_MMU_Set(MMU_ACCESS_FLASH, (uint32_t)&_fp_mem_start,
|
||||
p_addr, 64, p_numof, 0);
|
||||
Cache_Resume_ICache(autoload);
|
||||
|
||||
DEBUG("%s DCache MMU set paddr=%08x vaddr=%08x size=%d n=%u\n", __func__,
|
||||
p_addr, (uint32_t)&_fp_mem_start, CONFIG_ESP_FLASHPAGE_CAPACITY,
|
||||
p_numof);
|
||||
|
||||
if (res != ESP_OK) {
|
||||
LOG_TAG_ERROR("flashpage",
|
||||
"Could not map MMU pages in DCache, error: %d\n", res);
|
||||
}
|
||||
#else
|
||||
uint32_t p_mmu = ((uint32_t)&_fp_mem_start - SOC_DROM_LOW) / SPI_FLASH_MMU_PAGE_SIZE;
|
||||
|
||||
while (p_numof--) {
|
||||
uint32_t p_flash = p_addr / SPI_FLASH_MMU_PAGE_SIZE;
|
||||
DEBUG("%s map MMU page %"PRIu32" @0x%08"PRIx32" to "
|
||||
"flash page %"PRIu32" @0x%08"PRIx32"\n", __func__,
|
||||
p_mmu, (p_mmu * SPI_FLASH_MMU_PAGE_SIZE) + SOC_DROM_LOW,
|
||||
p_flash, p_flash * SPI_FLASH_MMU_PAGE_SIZE);
|
||||
SOC_MMU_DPORT_PRO_FLASH_MMU_TABLE[p_mmu] = SOC_MMU_PAGE_IN_FLASH(p_flash);
|
||||
p_addr += SPI_FLASH_MMU_PAGE_SIZE;
|
||||
p_mmu++;
|
||||
}
|
||||
#endif
|
||||
irq_restore(state);
|
||||
|
||||
if (IS_ACTIVE(ENABLE_DEBUG)) {
|
||||
spi_flash_mmap_dump();
|
||||
}
|
||||
}
|
||||
|
||||
void flashpage_erase(unsigned page)
|
||||
{
|
||||
assert(page < FLASHPAGE_NUMOF);
|
||||
|
||||
uint32_t flash_addr = _fp_flash_start + (page * FLASHPAGE_SIZE);
|
||||
|
||||
DEBUG("%s erase page in flash @0x%08"PRIx32"\n", __func__, flash_addr);
|
||||
|
||||
int res = spi_flash_erase_range(flash_addr, FLASHPAGE_SIZE);
|
||||
if (res != ESP_OK) {
|
||||
LOG_TAG_ERROR("flashpage", "Could not erase page %u, error %d\n",
|
||||
page, res);
|
||||
}
|
||||
}
|
||||
|
||||
void flashpage_write(void *target_addr, const void *data, size_t len)
|
||||
{
|
||||
DEBUG("%s write %u byte from @%p to @%p\n",
|
||||
__func__, len, data, target_addr);
|
||||
|
||||
/* assert multiples of FLASHPAGE_WRITE_BLOCK_SIZE are written */
|
||||
assert(!(len % FLASHPAGE_WRITE_BLOCK_SIZE));
|
||||
|
||||
/* ensure writes to flash are aligned */
|
||||
assert(!((unsigned)target_addr % FLASHPAGE_WRITE_BLOCK_ALIGNMENT));
|
||||
|
||||
/* ensure the length doesn't exceed the actual flash size */
|
||||
assert(((unsigned)target_addr + len) <=
|
||||
(CPU_FLASH_BASE + (FLASHPAGE_SIZE * FLASHPAGE_NUMOF)));
|
||||
|
||||
uint32_t flash_addr = ((uint32_t)target_addr - (uint32_t)&_fp_mem_start) + _fp_flash_start;
|
||||
|
||||
DEBUG("%s write to CPU address @%p (flash @0x%08"PRIx32")\n",
|
||||
__func__, target_addr, flash_addr);
|
||||
|
||||
int res = spi_flash_write(flash_addr, data, len);
|
||||
if (res != ESP_OK) {
|
||||
LOG_TAG_ERROR("flashpage", "Could not write to CPU address @%p "
|
||||
"(flash @0x%08"PRIx32"), error %d\n",
|
||||
target_addr, flash_addr, res);
|
||||
}
|
||||
}
|
||||
|
||||
unsigned flashpage_first_free(void)
|
||||
{
|
||||
/* _end_fw is page aligned */
|
||||
return flashpage_page(&_end_fw);
|
||||
}
|
||||
|
||||
unsigned flashpage_last_free(void)
|
||||
{
|
||||
// return flashpage_page((const void *)SOC_DROM_HIGH) - 1;
|
||||
return flashpage_page((void *)(CPU_FLASH_BASE + CONFIG_ESP_FLASHPAGE_CAPACITY)) - 1;
|
||||
}
|
||||
@ -289,6 +289,11 @@ static NORETURN void IRAM system_init (void)
|
||||
print_board_config();
|
||||
#endif
|
||||
|
||||
#if IS_USED(MODULE_PERIPH_FLASHPAGE)
|
||||
extern void esp_flashpage_init(void);
|
||||
esp_flashpage_init();
|
||||
#endif
|
||||
|
||||
#if IS_USED(MODULE_MTD)
|
||||
/* init flash drive */
|
||||
extern void spi_flash_drive_init (void);
|
||||
|
||||
@ -150,12 +150,22 @@ TEST_EXTRA_FILES += $(FLASHFILE) $(BINDIR)/partitions.bin $(BOOTLOADER_BIN)
|
||||
# table setting PARTITION_TABLE_CSV.
|
||||
PARTITION_TABLE_CSV ?= $(BINDIR)/partitions.csv
|
||||
|
||||
ifneq (,$(filter periph_flashpage_in_address_space,$(USEMODULE)))
|
||||
$(BINDIR)/partitions.csv: $(FLASHFILE)
|
||||
$(Q)printf "\n" > $(BINDIR)/partitions.csv
|
||||
$(Q)printf "nvs, data, nvs, 0x9000, 0x6000\n" >> $@
|
||||
$(Q)printf "phy_init, data, phy, 0xf000, 0x1000\n" >> $@
|
||||
$(Q)printf "flashpage, data, phy, $(FLASHPAGE_ADDR_START), $(FLASHPAGE_CAP)\n" >> $@
|
||||
$(Q)printf "factory, app, factory, $(FLASHFILE_POS), " >> $@
|
||||
$(Q)ls -l $< | awk '{ print $$5 }' >> $@
|
||||
else
|
||||
$(BINDIR)/partitions.csv: $(FLASHFILE)
|
||||
$(Q)printf "\n" > $(BINDIR)/partitions.csv
|
||||
$(Q)printf "nvs, data, nvs, 0x9000, 0x6000\n" >> $@
|
||||
$(Q)printf "phy_init, data, phy, 0xf000, 0x1000\n" >> $@
|
||||
$(Q)printf "factory, app, factory, $(FLASHFILE_POS), " >> $@
|
||||
$(Q)ls -l $< | awk '{ print $$5 }' >> $@
|
||||
endif
|
||||
|
||||
$(BINDIR)/partitions.bin: $(PARTITION_TABLE_CSV)
|
||||
$(Q)python3 $(RIOTTOOLS)/esptools/gen_esp32part.py --verify $< $@
|
||||
|
||||
@ -7,6 +7,7 @@ FEATURES_OPTIONAL += periph_flashpage_pagewise
|
||||
FEATURES_OPTIONAL += periph_flashpage_rwee
|
||||
|
||||
USEMODULE += od
|
||||
USEMODULE += od_string
|
||||
USEMODULE += shell
|
||||
|
||||
# avoid running Kconfig by default
|
||||
|
||||
@ -1,5 +1,6 @@
|
||||
# this file enables modules defined in Kconfig. Do not use this file for
|
||||
# application configuration. This is only needed during migration.
|
||||
CONFIG_MODULE_OD=y
|
||||
CONFIG_MODULE_OD_STRING=y
|
||||
CONFIG_MODULE_PERIPH_FLASHPAGE=y
|
||||
CONFIG_MODULE_SHELL=y
|
||||
|
||||
@ -81,31 +81,9 @@ static int getpage(const char *str)
|
||||
}
|
||||
|
||||
#ifdef MODULE_PERIPH_FLASHPAGE_PAGEWISE
|
||||
static void dumpchar(uint8_t mem)
|
||||
{
|
||||
if (mem >= ' ' && mem <= '~') {
|
||||
printf(" %c ", mem);
|
||||
}
|
||||
else {
|
||||
printf(" ?? ");
|
||||
}
|
||||
}
|
||||
|
||||
static void memdump(void *addr, size_t len)
|
||||
{
|
||||
unsigned pos = 0;
|
||||
uint8_t *mem = (uint8_t *)addr;
|
||||
|
||||
while (pos < (unsigned)len) {
|
||||
for (unsigned i = 0; i < LINE_LEN; i++) {
|
||||
printf("0x%02x ", mem[pos + i]);
|
||||
}
|
||||
puts("");
|
||||
for (unsigned i = 0; i < LINE_LEN; i++) {
|
||||
dumpchar(mem[pos++]);
|
||||
}
|
||||
puts("");
|
||||
}
|
||||
od_hex_dump (addr, len, LINE_LEN);
|
||||
}
|
||||
|
||||
static void dump_local(void)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user