To be able to reconfigure the PLL multiplier in clock configuration, the existing value has to be reset first. This becomes necessary when changing the core clock, e.g. when booting with riotboot an application that uses USB.
To allow CPU specific definitions in `cpu.h`, `riscv_common/cpu.h` is renamed to ``riscv_common/cpu_common.h` and included in new `cpu.h` files for FE310 and GD32V.
19450: cpu/esp32: fix compilation issues with GCC 12.2 r=benpicco a=gschorcht
### Contribution description
This PR provides the changes in `cpu/esp32` and `cpu/esp_common` to fix the compilation issues with GCC v12.2. It is required as the first step in the preparation of the upgrade to ESP-IDF version 5.1.
**Please note**: Insead of fixing the ESP-IDF 4.4 code itself by a big bunch of patches to fix the compilation problems with GCC v12.2, it temporarily disables some warnings. The reason is that the ESP-IDF 5.1 requires GCC v12.2 and should be fixed for this compiler version by the vendor.
### Testing procedure
Green CI
The change were already tested with all ESP-specific modules like `esp_now`, `esp_wifi`, `esp_spi` and `esp_ble` for all supported ESP platforms.
### Issues/PRs references
Prerequisite for https://github.com/RIOT-OS/riotdocker/pull/227
Fixes issue #19421
19476: native/syscalls: rename real_clock_gettime to clock_gettime r=benpicco a=Teufelchen1
### Contribution description
When compiling RIOT for native using a recent LLVM and enabling ASAN, one might encounter "Duplicated symbol".
This is due to a name clash with `real_clock_gettime()` in compiler-rt from [LLVM](f50246da65), I renamed RIOTs `real_clock_gettime` and just default to the posix function `clock_gettime`. The wrapper existed, most likely, for consistency only.
(The best solution would probably to convince the LLVM folks to declare their symbol as `static` and refactor a bit)
### Testing procedure
Passing CI should be enough.
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Co-authored-by: Teufelchen1 <bennet.blischke@haw-hamburg.de>
19436: cpp11-compat: thread::sleep_for in microseconds r=benpicco a=kfessel
### Contribution description
after reviewing #19369 i found that there is a conversion to nanoseconds just to convert it to microseconds some instrunctions later for ztimer64_usec to handle it this removes one of the conversions (convert once direct to microseconds)
### Testing procedure
run the cpp tests
### Issues/PRs references
#19369
Co-authored-by: Karl Fessel <karl.fessel@ovgu.de>
19447: boards/nucleo-f429zi: Provide 2nd timer r=benpicco a=maribu
### Contribution description
- Add a common timer config with two (instead of only one) timer using TIM2 + TIM5
- Mostly copy-pasting the cfg_timer_tim2.h and cfg_timer_tim5.h together
- Make use of that for the `nucleo-f429zi`
### Testing procedure
E.g. `tests/periph_timer`, but also grepping for TIM2 and TIM5 in `boards/nucleo-f429zi/include/periph_conf.h` to detect any conflict e.g. between PWM and timer config.
### Issues/PRs references
None
Co-authored-by: Marian Buschsieweke <marian.buschsieweke@ovgu.de>
19389: drivers/usbdev_synopsys_dwc2: add GD32V support r=bergzand a=gschorcht
### Contribution description
This PR provides the GD32V support in `drivers/usbdev_synopsys_dwc2`. It also includes some cleanup and bug fixes.
To support GD32V (CID 1.000) the PR includes the following changes:
- XFRC interrupts are also used in Non-DMA mode to complete a transfer
- SETUP phase done (STUP) interrupt is used in Non-DMA mode
- additional XFRC interrupts in SETUP stage are ignored
- RX FIFO handling doesn't complete a transfer anymore and is handled directly in ISR
- OTG interrupt handling added
The following fixes, improvements and cleanup has been added:
- USB OTG HS definition dependencies for platforms that don't support USB OTG HS
- thread context switch at ISR exit was added for all platforms
- units in USB FIFO size definitions are clarified
- USB EP number as defined in CMSIS is used
- FIFO allocation documentation is improved
- power modes for STM32 are fixed
- CID/HW debug info added
The PR could be split into a PRs with cleanups and improvements and a PR with GD32V support if necessary.
### Testing procedure
```
BOARD=sipeed-longan-nano make -j8 -C tests/shell
```
should work with `stdio_cdc_acm`.
`periph_usbdev` should still work for other platforms. The PR was tested with `tests/usbus_cdc_ecm` together with `stdio_cdc_acm` if possible:
```
esp32s2 FS CID: 0000, HWREV: 4f54400a, HWCFG: 224dd930 (esp32s2-devkit)
esp32s3 FS CID: 0000, HWREV: 4f54400a, HWCFG: 224dd930 (esp32s3-devkit)
efm32gg12 FS CID: 0000, HWREV: 4f54330a, HWCFG: 228f5910 (sltb009a)
gd32vf103cb FS CID: 1000, HWREV: 00000000, HWCFG: 00000000 (sipeed-longan-nano)
stm32f407vg FS CID: 1200, HWREV: 4f54281a, HWCFG: 229dcd20 (stm32f4discovery)
stm32f429zi HS CID: 1100, HWREV: 4f54281a, HWCFG: 229ed590 (stm32f429i-disc1)
stm32f439zi FS CID: 1200, HWREV: 4f54281a, HWCFG: 229dcd20 (nucleo-f439ze)
stm32f446ze FS CID: 2000, HWREV: 4f54320a, HWCFG: 229ed520 (nucleo-f446ze)
stm32f723ie FS CID: 3000, HWREV: 4f54330a, HWCFG: 229ed520 (stm32f723e-disco)
stm32f723ie HS CID: 3100, HWREV: 4f54330a, HWCFG: 229fe1d0 (stm32f723e-disco)
stm32f746ng FS CID: 2000, HWREV: 4f54320a, HWCFG: 229ed520 (stm32f746g-disco)
stm32f746ng HS CID: 2100, HWREV: 4f54320a, HWCFG: 229fe190 (stm32f746g-disco)
stm32f767zi FS CID: 2000, HWREV: 4f54320a, HWCFG: 229ed520 (nucleo-f767zi)
```
Boards with HS interfaces were tested in DMA and none-DMA mode.
### Issues/PRs references
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
After changing IN EPs also to use XFRC (Transfer Complete) interrupts in non-DMA mode, the TXFE (TX FIFO Empty) interrupt is no longer needed to signal the completion of an IN transfer.
XFRC (Transfer Complete) interrupts are now also used for OUT EPs in non-DMA mode. RXFLVL (RX FIFO Level) interrupts are no longer used to signal completed transfers, but only to copy data from FIFO to memory and to set a flag indicating that a SETUP stage is in progress. STUP (SETUP phase done) interrupts are then used to signal a completed SETUP stage and to reset the flags that indicates the SETUP stage. The flag that indicates the SETUP stage in progress is used to ignore additional XFRC interrupts for EP0 during the SETUP stage.
XFRC (Transfer Complete) interrupts are now also used for IN EPs in non-DMA mode. TXFE (TX FIFO Empty) interrupts are not necessarily needed but are still enabled.
Since the USB OTG FIFO sizes are partly defined in 32-bit words and partly in bytes, the documentation of the of the USB OTG FIFO size definitions is extended by the respective unit.
Since the USB OTG FIFO sizes are partly defined in 32-bit words and partly in bytes, the documentation of the of the USB OTG FIFO size definitions is extended by the respective unit.
Since the USB OTG FIFO sizes are partly defined in 32-bit words and partly in bytes, the documentation of the of the USB OTG FIFO size definitions is extended by the respective unit.
The USB device driver ISR sets a thread flag of the waiting USBUS thread to indicate that it has to handle a USB device driver event. However, setting a thread flag only sets `sched_context_switch_request` to indicate that a thread context switch would be required, but it is not executed. Therefore, for STM32 MCUs, `cortexm_isr_end` was called to execute the context switch. Since the driver is also used by other platforms, this call is replaced by a direct call of `thread_yield_higher` if required. NOTE: For ESP32x SoC, such a thread context switch is implicitly executed at the end of each ISR if necessary.
If the MCU/board has only an USB OTG FS peripheral or only an USB OTG HS peripheral, it should only need to specify the USB OTG FS definitions such as the number of EPs or the FIFO sizes or only the USB OTG HS definitions. This commit cleans up the code so that it is translatable without the respective definitions.
19471: drivers/periph_usbdev: fix set device address r=bergzand a=gschorcht
### Contribution description
This PR allows to define when the device address is set on receipt of a SETUP with `SET ADDRESS Request`. It fixes the problem with enumeration of the Synopsys DWC2 USB OTG Core due to the wrong time of setting the device address.
Especially, it fixes the problem that the enumeration fails completely for the `stm32f723e-disco` board with CDC ECM if CDC ACM is not used and the additional reset cycles during the enumeration for a couple of platforms such as ESP32-S2 and ESP32-S3.
**Background**
The address in the USB device can be set either directly after the SETUP stage on receipt of the `SET ADDRESS Request` or after the associated STATUS stage. When the USB device address has to be set depends on the hardware implementation.
**Solution**
To control the time of setting the device address, a new define `USBDEV_SET_ADDR_AFTER_STATUS` is introduced.
If `USBDEV_SET_ADDR_AFTER_STATUS` has the value 1 (default), the address is set in the USB device after the STATUS stage. Since this is the default, existing `periph_usbdev` drivers shouldn't be affected. Overwriting `USBDEV_SET_ADDR_AFTER_STATUS` with 0 in `periph_cpu.h` or in driver header file let the address set directly after the SETUP stage.
### Testing procedure
Use `tests/usbus_cdc_ecm`:
For `stm32f723e-disco` the enumeration doesn't work at all without this PR and works reliable with this PR.
```
USEMODULE='periph_usbdev_hs_utmi' BOARD=stm32f723e-disco make -C tests/usbus_cdc_ecm flash
```
For any ESP32-S2 or ESP32-S3 board, the enumeration requires an addition reset cycle in every third or fourth enumeration without this PR and doesn't require any reset cycle with this PR.
```
BOARD=esp32s2-devkit make -C tests/usbus_cdc_ecm flash
```
Other platforms should still work with this PR, for example ATSAM platform:
```
BOARD=arduino-mkr1000 make -C tests/usbus_cdc_ecm flash
```
### Issues/PRs references
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Use symbol `USBDEV_SET_ADDR_AFTER_STATUS` to determine whether the device address has to be set directly after SETUP stage or after the associated STATUS stage.
