Teufelchen1
0e839654e8
cpu/riscv: Add PMP driver
2023-06-28 11:55:34 +02:00
Gunar Schorcht
2ae7566a89
cpu/riscv_common: rename cpu.h to cpu_common.h
...
To allow CPU specific definitions in `cpu.h`, `riscv_common/cpu.h` is renamed to ``riscv_common/cpu_common.h` and included in new `cpu.h` files for FE310 and GD32V.
2023-04-18 06:20:14 +02:00
Benjamin Valentin
ea917f4b07
cpu: cpu_print_last_instruction() -> cpu_get_caller_pc()
2022-09-15 10:49:56 +02:00
PeterKietzmann
6215b7e630
cpu/riscv_common: add puf_sram feature
2022-02-16 15:18:37 +01:00
Benjamin Valentin
41a5b7ef7a
core: change return type of irq_is_in(), irq_is_enabled() to bool
...
This only cleans up the API, no change in behavior or users of the API
is expected.
2021-12-08 15:53:15 +01:00
Jan Romann
3056b89252
cpu/riscv_common: uncrustify
2021-11-19 00:20:12 +01:00
Benjamin Valentin
3e20e939c6
cpu: drop cpu_init() from public headers
...
Boards are no longer supposed fo call the function, so drop it from
public header files.
2021-10-18 17:31:26 +02:00
Jean-Pierre De Jesus DIAZ
22a7e1af03
cpu/riscv_common: fix doxygen grouping warnings
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Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
2021-09-11 12:45:15 +02:00
Hauke Petersen
9a5edcf839
cpu/riscv: implement irq_is_enabled()
2021-08-25 08:01:05 +02:00
benpicco
025770968b
Merge pull request #16036 from bergzand/pr/gd32vf103/initial
...
gd32v/seeedstudio-gd32: Initial support
2021-08-25 00:38:00 +02:00
f2787448e1
cpu/riscv_common: Move MCAUSE defines to riscv_common
2021-08-24 14:30:23 +02:00
48aa533639
cpu/riscv_common: Add CLIC peripheral driver
...
The CLIC is a next generation interrupt controller for the RISC-V
architecture.
Co-authored-by:
2021-08-24 10:30:18 +02:00
9239c2fe14
cpu/riscv_common: Add bit set and clear functions
2021-08-24 10:30:15 +02:00
Jan Romann
4384795cb9
treewide: Remove excessive newlines
2021-08-13 19:50:38 +02:00
0b2810a856
riscv_common: make thread_yield_higher IRQ compatible
2021-02-08 11:04:18 +01:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common
2021-02-05 09:32:19 +01:00
