MrKevinWeiss
e0fdc3c16c
*Kconfig*: Modify Kconfig to remove dep model
2024-03-27 10:28:12 +01:00
Gunar Schorcht
e1ea18fea2
cpu/riscv_common: remove picolibc from blacklisting in CI
2023-08-07 13:21:40 +02:00
PeterKietzmann
6215b7e630
cpu/riscv_common: add puf_sram feature
2022-02-16 15:18:37 +01:00
chrysn
d391b1c5f4
cpu/riscv_common: Enable Rust applications
...
This contains a workaround for
https://github.com/rust-lang/rust-bindgen/issues/1555 (withouot which
bindgen would fail, with little information helping remedy the cause)
2022-01-14 13:42:32 +01:00
chrysn
a2e1b92e1d
makefiles: Define RUST_TARGET for use with Cargo / Rust
...
For RISC-V and Cortex-M-not-3, triples are known and have worked in some
configuration, but do not work at the moment and stay disabled until the
reference platforms (native, M3) have been established well.
2021-12-14 12:55:13 +01:00
Leandro Lanzieri
cf753c6790
cpu/riscv_common: model Kconfig
2021-10-01 11:26:15 +02:00
Karl Fessel
fe03c4c059
cpu/riscv,gd32: match Kconfig to Makefile changes
2021-09-22 15:50:28 +02:00
Benjamin Valentin
a9c83017ee
cpu/riscv_common: only select PLIC for fe310
...
Not every RISC-V implements that interrupt controller, gd32v uses
CLIC instead.
2021-08-25 10:49:47 +02:00
2692957c0e
riscv_common: Refactor common fe310 code to riscv_common
2021-02-05 09:32:19 +01:00
