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mirror of https://github.com/RIOT-OS/RIOT.git synced 2024-12-29 04:50:03 +01:00
Commit Graph

74 Commits

Author SHA1 Message Date
Gunar Schorcht
cfbda4022a cpu/gdv32: add pm_layered support 2023-01-24 00:52:02 +01:00
Gunar Schorcht
b02ffb21b8 cpu/gd32v: use NMSIS SDK package 2023-01-24 00:52:02 +01:00
Gunar Schorcht
ced6344651 cpu/gd32v: add periph_gpio_irq support 2023-01-23 22:51:35 +01:00
Gunar Schorcht
13e4ea4be1 boards/sipeed-longan-nano: initial support 2023-01-23 18:59:32 +01:00
Gunar Schorcht
31604da8fe boards/common: add common definitions for GD32VF103 boards 2023-01-23 18:59:32 +01:00
Gunar Schorcht
19420d6595 cpu/gd32v: add periph_rtc support 2023-01-22 17:53:44 +01:00
bors[bot]
fb603f2660
Merge #18459 #18724 #19081 #19082 #19136
18459: makefiles/suit: make it possible to accept multiple SUIT keys r=miri64 a=benpicco



18724: nanocoap_sock: implement DTLS socket r=miri64 a=benpicco



19081: sys/stdio_udp: add stdio over UDP r=benpicco a=benpicco



19082: core/init: add early_init() r=benpicco a=benpicco



19136: CI: re-add "synchronize" event to check-labels r=miri64 a=kaspar030



Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Co-authored-by: Benjamin Valentin <benjamin.valentin@bht-berlin.de>
Co-authored-by: Kaspar Schleiser <kaspar@schleiser.de>
2023-01-13 13:50:55 +00:00
Gunar Schorcht
72d11d84b8 boards/seeedstudio-gd32: extend Kconfig by clock configuration
The configuration whether a HXTAL is present and what its clock frequency is will be added to Kconfig. Since it is the only GD32V board at the moment, the configuration is added to the Kconfig of the board, but should be moved to a common Kconfig later when more GD32V boards are added.
2023-01-09 21:51:54 +01:00
Benjamin Valentin
124b849503 cpu: call early_init() 2023-01-08 22:26:12 +01:00
Gunar Schorcht
f4d6b2d642 cpu/gd32v: fix clock setting
`CONFIG_BOARD_HAS_HXTAL` is used to indicate that the board has an HXTAL connected. If the HXTAL is present, it is used as PLL clock source. But if the HXTAL is not present, the half IRC8M clock should be used as PLL clock source and must not be disabled at the end of clock settings. Using IRC8M clock as PLL clock source also requires another PLL multiplication factor.
2023-01-08 11:32:28 +01:00
Gunar Schorcht
e4010f7445 cpu/gd32v: fix clock setting
`CLOCK_HXTAL` is a value and not a flag, so that shifting to the left changes anything in the register but does not set the PLLSEL bit. `RCU_CFG0_PLLSEL_Msk` has to be used instead to set the PLLSEL bit.
2023-01-08 10:42:01 +01:00
Gunar Schorcht
dd0593a3c8 cpu/gd32v: fix clock setting
Setting the `RCU_CTL` register just to the IRC8M bit also removes the IRC8M calibration and trim adjust value in this register. Therefore IRC8M calibration and trim adjust value have to be preserved and the IRC8M has to be set.
2023-01-08 10:42:01 +01:00
Benjamin Valentin
7abaae7bbd treewide: fix typos 2022-09-15 12:12:23 +02:00
Marian Buschsieweke
bae91c1660
Merge pull request #17723 from benpicco/periph_timer_periodic-set_stopped
drivers/periph/timer: add TIM_FLAG_SET_STOPPED flag
2022-05-03 12:06:37 +02:00
Benjamin Valentin
7ed69cc08a cpu/gd32v: timer: implement TIM_FLAG_SET_STOPPED 2022-04-28 13:27:59 +02:00
Ollrogge
41f961a197 periph/flashpage: Add _in_address_space feature 2022-03-17 19:45:54 +01:00
Benjamin Valentin
55454e9301 cpu/gd32v: timer: add ; after DEBUG() 2021-12-08 18:30:24 +01:00
Benjamin Valentin
90a6d90df8 cpu/gd32v: uart: fix function parameter 2021-11-18 10:14:51 +01:00
Leandro Lanzieri
a015508e77
cpu/gd32v: model Kconfig 2021-10-01 11:26:15 +02:00
Karl Fessel
fe03c4c059 cpu/riscv,gd32: match Kconfig to Makefile changes 2021-09-22 15:50:28 +02:00
Karl Fessel
645cb04c4d cpu/riscv,gd32v: add CPU_ARCH, CPU_CORE information
adds CPU_ARCH to riscv_common preparing to handle it like cortex-m does
adds CPU_CORE to gd32v
2021-09-22 14:39:44 +02:00
Benjamin Valentin
a75ae3c938 cpu/riscv_common: move C lib selection to common place 2021-08-25 10:53:00 +02:00
Benjamin Valentin
e92a4b9628 cpu/gd32v: enable periph_timer_periodic 2021-08-25 10:48:48 +02:00
3d470b0c12 cpu/gd32v: Initial include of the GD32VF103 device
This adds support for the gd32v class devices from Gigadevice. The
gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as
the stm32f1 devices

Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-08-24 14:30:23 +02:00