Benjamin Valentin
5d111e71aa
boards: drop board_init() from board.h
2022-02-25 15:08:58 +01:00
0a45ac5fa1
boards/hifive1*: use common clock configuration
2020-12-17 15:53:31 +01:00
cdbb3e025a
cpu/fe310: boards/hifive1*: use IS_ACTIVE where possible
2020-09-09 14:14:39 +02:00
ace160a2a3
boards/hifive1: use MHZ utility macro for clock frequency
2020-09-09 14:14:39 +02:00
c190426a0e
boards/hifive1*: fix clock configuration
2020-09-09 14:14:39 +02:00
Francisco Molina
442b11d0ee
cpu/fe310: add unified rtt configuration
2020-08-12 14:46:59 +02:00
7acf81552a
boards/hifive1* cpu/fe310: improve clock customization
2020-08-06 15:59:34 +02:00
8405fbe611
boards/hifive1*: provide and configure SPI feature
2020-01-11 13:06:39 +01:00
b42cf186fe
boards/hifive1*: remove gpio interrupt definition
...
This macro is now defined in periph_cpu.h
2020-01-10 16:41:33 +01:00
97ef5d53de
boards/hifive1*: rework clock configuration
2020-01-10 16:41:33 +01:00
39cf4d38c1
boards/hifive1*: move xtimer definitions to board.h
2020-01-10 16:41:32 +01:00
876824201c
boards/hifive1*: apply new UART configuration scheme
2019-12-20 15:22:09 +01:00
Benjamin Valentin
0ea2cbf1eb
boards: remove RTT_NUMOF/RTC_NUMOF
...
Those macros are defined but never used.
2019-11-08 14:20:33 +01:00
kenrabold
6391913a15
board/hifive1: minor changes for FE310_G000 CPU
...
Minor changes to support both HiFive1 and HiFive1B boards and their respective CPUs
2019-07-19 13:25:17 -07:00
Tristan Bruns
8d50b8cc60
boards/hifive1: fix CLOCK_CORECLOCK
2019-01-17 17:21:09 +01:00
kenrabold
db4d67c4fd
make: add hifive1 to BOARD_INSUFFICIENT_MEMORY
...
Added HiFive1 to BOARD_INSUFFICIENT_MEMORY list for examples and tests that are too big to fit
build: fixed missing syscall and cpuid failures
Added missing syscall stubs for nanostubs and fixed compile error with cpuid periph
build: fixed whitespace error
build: add hifive1 to more BOARD_INSUFFICIENT_MEMORY
doc: fixed doxygen warnings
Addressed Doxygen warnings in source file comments
doc: more doxygen fixes
doc: even more doxygen fixes
doc: more changes
build: fix pedantic and rdci_simple build failures
make: exclude lua
2018-05-29 16:27:53 -07:00
kenrabold
619dd9ee3b
board/hifive1: add RISC-V board HiFive1
...
Add new RISC-V board HiFive1 from SiFive based on FE310 CPU
2018-05-29 15:21:45 -07:00
