The 10 bit DAC on the lpc23xx is very simple.
It only has one channel and can only be mapped to a single pin (P0.26).
After setting the pin mode to DAC no further configuration in needed.
puf_sram only relies on an uninitialized chunk of memory.
This means to enable it we just have to hook up puf_sram_init().
All memory after __bss_end should be uninitialized at startup, so
just use that.
Enable IDLE and Deep Powerdown mode.
IDLE is pretty straightforward - insteady of busy waiting, the CPU will
enter an idle state from which it will resume on any event.
Deep Power Down shuts off the entite system except for the battery backup
power domain.
That means the CPU will reset on resume and can be woken by e.g. RTC.
SLEEP and POWERDOWN disable the PLL and the PLL and Flash respectively.
This requires some proper wake-up handling.
Since this turned out to be a major time sink and those modes are never
currently never used in RIOT outside of tests, I left this as an exercise
for a future reader.
This converts the hard-coded UART driver to the new ways.
- allow the board to configure the RX & TX pins
- allow for more than one UART
- allow setting the baudrate
- implement poweron()/poweroff() functions
Currently the cpu/lpc2387 init code hard-codes a 16 MHz
external oscillator.
Instead, calculate the PLL multiplier based on the board define
and also allow to run without an external oscillator.
At the time of configuration, the pthread-reaper uses '164' bytes of
stack when 'idle' stack is only '160'. By having double it gives some
margin.
ps
pid | name | state Q | pri | stack ( used) | base addr | current
1 | idle | pending Q | 15 | 160 ( 128) | 0x4000007c | 0x4000009c
2 | main | running Q | 7 | 2560 ( 1232) | 0x4000011c | 0x4000095c
3 | pthread-reaper | bl rx _ | 0 | 320 ( 164) | 0x40000bac | 0x40000c48
| SUM | | | 3040 ( 1524)
- Fixed documentation
- Use bitwise operation instead of multiplication and addition in `GPIO_PIN()`
- Allow GPIOs to be configured as input via `gpio_init()`
- Fixed bugs in `gpio_init_mux`:
- `0x01 << ((pin & 31) * 2)` was used before to generate the bitmask, but
this would shift by 62 to the left. Correct is `0x01 << ((pin & 15) * 2)`
(See [datasheet](https://www.nxp.com/docs/en/user-guide/UM10211.pdf) at
pages 156ff)
- Only one of the two bits was cleared previously
- Changed strategy to access GPIO pins:
- Previous strategy:
- Set all bits in FIOMASK except the one for the pin to control to
disable access to them
- Set/clear/read all pins in the target GPIO port (but access to all but
the target pin is ignored because of the applied FIOMASK)
- New strategy:
- Set/clear/read only the target pin
- Advantages:
- Only one access to a GPIO register instead of two
- Proven approach: Access to GPIOs on lpc2387 is mostly done by
accessing the GPIO registers directy (e.g. see the sht11 driver).
Those accesses never touch the FIOMASK register
- No unwanted side effects: Disabling all but one pin in a GPIO port
without undoing that seems not to be a good idea
- removed ISR_STACKSIZE define where unused (set to 0)
- removed thread_arch_isr_stack_usage(), thread_arch_isr_stack_start(),
and/or thread_arch_isr_stack_pointer() where not implemented
As discussed in #2725, this commit renames a number of stacksize constants to
better convey their intended usage. In addition, constants for thread priority
are given a `THREAD_` prefix. Changes are:
* KERNEL_CONF_STACKSIZE_PRINTF renamed to THREAD_EXTRA_STACKSIZE_PRINTF
* KERNEL_CONF_STACKSIZE_DEFAULT renamed to THREAD_STACKSIZE_DEFAULT
* KERNEL_CONF_STACKSIZE_IDLE renamed to THREAD_STACKSIZE_IDLE
* KERNEL_CONF_STACKSIZE_MAIN renamed to THREAD_STACKSIZE_MAIN
* Move thread stacksizes from kernel.h to thread.h, since the prefix changed
* PRIORITY_MIN renamed to THREAD_PRIORITY_MIN
* PRIORITY_IDLE renamed to THREAD_PRIORITY_IDLE
* PRIORITY_MAIN renamed to THREAD_PRIORITY_MAIN
* Move thread priorities from kernel.h to thread.h since the prefix has changed
* MINIMUM_STACK_SIZE renamed to THREAD_STACKSIZE_MINIMUM for consistency
