RIOT-OS uses part of Espressif ESP8266 RTOS SDK to build support for
this CPU. The SDK includes some vendor-provided closed source
pre-compiled libraries that we need to modify to adapt to RIOT-OS
usage. This library modifications was done once and uploaded to a fork
of the vendor repository and was provided as an environment variable.
This patch changes two things:
1. It installs the SDK as a RIOT PKG from the new pkg/esp8266_sdk
directory instead of requiring the user to download it separately.
2. It performs the library modifications (symbol renames) on the pkg
Makefile removing the need to use a fork with the modifications applied
and simplifying the SDK update and future modifications.
This change sets the SDK package version (git SHA) to the same one that
our fork was using as a parent in the vendor repository, meaning that
the output libraries are exactly the same as before.
Tested with
```
ESP8266_RTOS_SDK_DIR=/dev/null USEMODULE=esp_log_startup make -C tests/shell BOARD=esp8266-esp-12x flash
```
and verified that the program works. The boot message now includes:
```
ESP8266-RTOS-SDK Version v3.1-51-g913a06a9
```
confirming the SDK version used.
`/dev/null` in the test is just to make sure that no evaluation of
`ESP8266_RTOS_SDK_DIR` in make is affected by the environment variable
value which would be set to the SDK for people who followed the set up
instructions before this change.
Tested the checkout size:
```bash
$ du -hs build/pkg/esp8266_sdk/
124M build/pkg/esp8266_sdk/
```
If esp_idf_heap is not used, implement calloc through a custom wrapper
function on top of malloc to add overflow detection, which is not
present in the newlib forks with xtensa support yet.
The esp8266 CPU has actually two hardware UART peripherals. UART0 is
used by the boot ROM for flashing and serial output during boot,
typically at a baudrate of 74880 bps until the bootloader or application
sets the more standard 115200 baudrate. This UART0 device has two
possible pins for TXD, GPIO1 and GPIO2, which are both set to TXD by the
boot ROM. esp8266 modules will typically have GPIO1 labeled as the TX
pin, but it is possible to use GPIO2 for that purpose even while
flashing the device with esptool.py.
The second device, UART1, also has two options for TXD, GPIO2 and GPIO7,
and only one option for RXD, GPIO8. However, GPIO7 and GPIO8 are used
by the flash internally so those options are not very useful unless
maybe while running from IRAM with the flash disabled, for example for
a debugger over UART1.
This patch allows boards to override UART{0,1}_{R,T}XD in their
periph_conf.h to configure the uart selection. Defining UART1_TX will
make the UART_DEV(1) device available.
Tested with:
```CFLAGS='-DUART1_TXD=GPIO2' make -C tests/periph_uart BOARD=esp8266-esp-12x flash term```
* Connected one USB-UART to the standard GPIO1 and GPIO3 for flashing
and console. After flashing we see the manual test output at 115200
bps
* Connected a second USB-UART with RX to GPIO2 running at 74880.
Then run on the first console:
```
> init 1 74880
> send 1 hello
```
The word "hello" appears on the second UART connection.
Note that GPIO2 is used during boot for UART0's TX until the application
or bootloader set it to a regular GPIO, so some boot ROM messages at
74880 bps are visible. After running `init 1 74880` it is set to UART1's
TX.
In I2C, clock stretching occurs when the controller stops driving SCL
down but the peripheral continues to drive SCL down until the value of
SDA that is expected to be set by the peripheral is ready. This allows a
peripheral to communicate at a high speed but introduce a delay in the
response (like an ACK or read) in some specific situations. Not all I2C
peripherals require I2C stretching, and in many cases SCL is only an
input to these peripherals.
Clock stretching is the only situation where a peripheral may drive down
SCL, which technically makes SCL an open-drain with a pull-up like SDA.
However, if clock stretching is not needed, SCL can be configured as an
output removing the need for a pull-up and specially, allowing to use
as SCL GPIO pins that otherwise have a pull-down connected. In
particular, GPIO15 in the ESP8266 requires an external pull-down during
boot for the ESP8266 to boot from the flash.
This patch allows a board to define `I2C_CLOCK_STRETCH` to 0 to disable
clock stretching and allowing to use GPIO15 as SCL.
- Add `WORD_ALIGNED` attribute to potentially unaligned allocations
- Use intermediate cast to `uintptr_t` to silence false positives of
`-Wcast-align`
This is an implementation of the ESP32 SoftAP mode using the
`esp_wifi_ap` pseudomodule.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
Declare sched_active_thread and sched_active_pid locally in the ESP code for
now. Once the code is cleaned up to no longer tap into scheduler internals but
use the API instead, those can be dropped again.
