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30 Commits

Author SHA1 Message Date
Marian Buschsieweke
c3500eb6e0
tree wide: fix typos in comments found by codespell
This will not change generated binaries, only the Doxygen output and
source code will have less typos.
2023-05-02 09:52:06 +02:00
Gunar Schorcht
f979730730 cpu/gd32v: fix gpio_read in periph_gpio 2023-03-24 07:40:23 +01:00
Gunar Schorcht
5433daca32 cpu/gd32v/periph_i2c: interrupt based driver 2023-02-17 18:52:38 +01:00
bors[bot]
f341ad6c9c
Merge #17045 #19243
17045: sys/coding: add XOR based coding module r=benpicco a=benpicco



19243: cpu/gd32v: add periph_gpio_ll and periph_gpio_ll_irq support r=benpicco a=gschorcht

### Contribution description

This PR provides the `periph_gpio_ll` and `periph_gpio_ll_irq` support for GD32VF103. Level triggered interrupts are emulated.

`periph_gpio_ll_irq` could be split off from this PR as a separate PR if necessary.

### Testing procedure

Use any GD32V board and connect PA0 -> PB0 and PA1 -> PB1 where PA is the output port and PB the input port. With these connections `tests/periph_gpio_ll` should work.
```
BOARD=sipeed-longan-nano make -j8 -C tests/periph_gpio_ll flash term
```

If necessary, change the input and output pins by setting the environment variables and connect the corresponding pins, for example for `seeedstudio-gd32` PA1 -> PB8 and PA8 -> PB9:
```
PIN_OUT_0=1 PIN_OUT_1=8  PIN_IN_0=8 PIN_IN_1=9 BOARD=seedstudio-gd32 make -j8 -C tests/periph_gpio_ll flash term
```

### Issues/PRs references


Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
2023-02-07 17:39:20 +00:00
bors[bot]
dd2d336962
Merge #19240 #19248 #19255
19240: tools/doccheck: add simple exclude to doccheck r=benpicco a=kfessel

while doccheck runs for #19228 and #19220, i saw some spikes in memory consumption, turned out that was `grep -Evf dist/tools/doccheck/exclude_patterns` using about 2GB RAM. This PR changes that.

### Contribution description

add `exclude_simple`  to `doccheck` drived from `exclude patterns`
`sort`ed and `uniq`ued the simple excludes
removes no longer needed patterns from `exclude patterns`

simple excludes are string rules (no patterns just strings) 
how to apply these:
in this PR: 
*remove the path and line number from the rule
* that made some of them doubles of each other
* sorted and uniqued them. 
* this set of excludes is no longer path specific (an exception covers all paths but may of them still contain a file name)

another possible solution would be to have the excludes line number specific.

### Testing procedure

run `dist/tools/doccheck/check.sh`

compare memory consumption of 
master: `grep -Evf dist/tools/doccheck/exclude_patterns`
to 
this PR: `grep -Fvf dist/tools/doccheck/exclude_simple`

### Issues/PRs references



19248: cpu/gd32v: add periph_dac support r=benpicco a=gschorcht

### Contribution description

This PR provides the `periph_dac` support for GD32VF103.

### Testing procedure

`tests/periph_dac` should work on `sipeed-longan-nano` port on PA4 and PA5.

### Issues/PRs references

19255: boards/esp*: complete SD Card MTD config r=benpicco a=gschorcht

### Contribution description

This PR provides the remaining changes necessary to use the generic MTD SD Card configuration as described in PR #19216. 

This includes defining the MTD offset for SD cards, since the default `MTD_0` device always uses the internal flash device, and the completion of the configuration for the ESP32 boards with a SD card interface.

### Testing procedure

`tests/vfs_default` should work now with SD Cards:
```
main(): This is RIOT! (Version: 2023.04-devel-323-gfcc07)
mount points:
	/nvm0
	/sd0

data dir: /sd0
> vfs df 
Mountpoint              Total         Used    Available     Use%
/nvm0                3052 KiB        8 KiB     3044 KiB       0%
/sd0                 7580 MiB 3632148992 B   21089792 B      99%
```

### Issues/PRs references


Co-authored-by: Karl Fessel <karl.fessel@ovgu.de>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
2023-02-07 14:55:44 +00:00
Gunar Schorcht
0561e99b0a cpu/gd32v: add perip_gpio_ll_irq support 2023-02-07 12:19:49 +01:00
bors[bot]
af393878d1
Merge #19251 #19254
19251: tests/driver_dac_dds: fix output of sine and saw functions r=benpicco a=benpicco



19254: cpu/gd32v: add periph_rtc_mem support r=benpicco a=gschorcht

### Contribution description

This PR provides the `periph_rtc_mem` support for GD32VF103.

A modified version of this driver could also be used for STM32F1.

### Testing procedure

`tests/periph_rtt` should work on any GD32V board, for example:
```
BOARD=sipeed-longan-nano make -C tests/periph_rtt flash
```
```
Help: Press s to start test, r to print it is ready
START
main(): This is RIOT! (Version: 2023.04-devel-319-gebc86-cpu/gd32v/periph_rtc_mem)

RIOT RTT low-level driver test
RTT configuration:
RTT_MAX_VALUE: 0xffffffff
RTT_FREQUENCY: 32768

Testing the tick conversion
Trying to convert 1 to seconds and back
Trying to convert 256 to seconds and back
Trying to convert 65536 to seconds and back
Trying to convert 16777216 to seconds and back
Trying to convert 2147483648 to seconds and back
All ok

Initializing the RTT driver
RTC mem OK
This test will now display 'Hello' every 5 seconds

RTT now: 1
Setting initial alarm to now + 5 s (163841)
rtt_get_alarm() PASSED
RTC mem OK
```

### Issues/PRs references

Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
2023-02-07 07:33:48 +00:00
Gunar Schorcht
64663ee743 cpu/gd32v: add periph_dac support 2023-02-07 02:41:06 +01:00
Gunar Schorcht
dc5a1e9db0 cpu/gd32v: add periph_rtc_mem support 2023-02-06 22:22:01 +01:00
Gunar Schorcht
ae984b0bea cpu/gd32v: allow SPI pin remapping in config 2023-02-06 07:45:59 +01:00
Gunar Schorcht
aa55e3a5a1 cpu/gd32v: add gpio_ll support 2023-02-04 12:07:35 +01:00
Gunar Schorcht
f7949e42fd cpu/gd32v: add periph_adc support 2023-02-01 23:11:07 +01:00
Gunar Schorcht
42b683a89e cpu/gdv32: add SPI support 2023-02-01 02:37:54 +01:00
Gunar Schorcht
5355a2435c cpu/dg32v: add periph_i2c support 2023-01-31 20:12:04 +01:00
Gunar Schorcht
e9be9b4e75 cpu/gd32v: add periph_pwm support 2023-01-28 18:16:17 +01:00
Gunar Schorcht
0dfbdebaf7 cpu/gd32v: allow using TIMER0 as timer device 2023-01-28 17:46:45 +01:00
Gunar Schorcht
596d762806 cpu/gd32v: move TIMER_CHANNEL macros to header file 2023-01-28 17:39:06 +01:00
Gunar Schorcht
2c6e527339 cpu/gd32v: fix interrupt handling in periph_timer
When a timer is set, any pending interrupts must be cleared before the interrupt is enabled for the channel. Otherwise the interrupt would be triggered immediately when the timer is set.
2023-01-28 17:37:15 +01:00
Gunar Schorcht
4383e0ac6f cpu/gd32v: fix periph_flashpage doc group 2023-01-27 06:46:51 +01:00
Gunar Schorcht
0b6fc8833b cpu/gd32v: add periph_rtt support 2023-01-27 06:46:51 +01:00
bors[bot]
f85366ae60
Merge #19185 #19187
19185: cpu/gd32v: add periph_gpio_irq support r=gschorcht a=gschorcht

### Contribution description

This PR provides the `periph_gpio_irq` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103.

### Testing procedure

Use a GD32VF103 board and flash `tests/periph_gpio`. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board defintion and could be used for testing.
```
BOARD=seeedstudio-gd32 make -C tests/periph_gpio flash  (until PR #19170 is merged only `seeedstudio
```
With the GPIO PB8 and PB9 connected, the following test sequence should work:
```
> init_out 1 8
> init_int 1 9 2 0
GPIO_PIN(1, 9) successfully initialized as ext int
> set 1 8
INT: external interrupt from pin 9
> clear 1 8
INT: external interrupt from pin 9
```


### Issues/PRs references


19187: cpu/gd32v: add pm_layered support in periph_pm r=gschorcht a=gschorcht

### Contribution description

This PR provides the `pm_layered` support and is one of a bunch of follow up PRs that complete the peripheral drivers for GD32VF103.

Since the configuration of the deep sleep and the standby mode require the access CSR (control and status registers) of the MCU, the Nuclei-SDK NMSIS is added as package which provides a low-level interface for Nuclei-based RISC-V MCUs.

### Testing procedure

The best way to test it is to rebase this PR onto PR #19186 and to flash `tests/periph_pm` to any GD32VF103 board. Note: The Sipeed Longan Nano works also with `seeedstudio-gd32` board definition and could be used for testing.
```
BOARD=seeedstudio-gd32 make -C tests/periph_pm flash
```
The test output should be:
```
main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test)
...
mode 0 blockers: 1 
mode 1 blockers: 2 
mode 2 blockers: 0 
Lowest allowed mode: 2
```
Using command the `set_rtc 1 5` command should let the MCU deep sleep for 5 seconds
```
> set_rtc 1 5
Setting power mode 1 for 5 seconds.
␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀␀> 
```
while command `set_rtc 1 5` should set the MCU into the standby mode which is left with restart.
```
> set_rtc 0 5
Setting power mode 0 for 5 seconds.
main(): This is RIOT! (Version: 2023.04-devel-174-g7dc91-cpu/gd32v/periph_pm_test)
...
mode 0 blockers: 1 
mode 1 blockers: 2 
mode 2 blockers: 0 
Lowest allowed mode: 2
> 
```
The garbage on UART interface after deep sleep is caused by the clock synchronisation that becomes necessary after deep sleep and is the same as for other boards.

### Issues/PRs references

Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
2023-01-24 14:38:28 +00:00
Gunar Schorcht
cfbda4022a cpu/gdv32: add pm_layered support 2023-01-24 00:52:02 +01:00
Gunar Schorcht
ced6344651 cpu/gd32v: add periph_gpio_irq support 2023-01-23 22:51:35 +01:00
Gunar Schorcht
19420d6595 cpu/gd32v: add periph_rtc support 2023-01-22 17:53:44 +01:00
Benjamin Valentin
7abaae7bbd treewide: fix typos 2022-09-15 12:12:23 +02:00
Benjamin Valentin
7ed69cc08a cpu/gd32v: timer: implement TIM_FLAG_SET_STOPPED 2022-04-28 13:27:59 +02:00
Benjamin Valentin
55454e9301 cpu/gd32v: timer: add ; after DEBUG() 2021-12-08 18:30:24 +01:00
Benjamin Valentin
90a6d90df8 cpu/gd32v: uart: fix function parameter 2021-11-18 10:14:51 +01:00
Leandro Lanzieri
a015508e77
cpu/gd32v: model Kconfig 2021-10-01 11:26:15 +02:00
3d470b0c12 cpu/gd32v: Initial include of the GD32VF103 device
This adds support for the gd32v class devices from Gigadevice. The
gd32vf103 contains an 108 MHz RISC-V core with similar peripherals as
the stm32f1 devices

Co-authored-by: Benjamin Valentin <benjamin.valentin@ml-pa.com>
2021-08-24 14:30:23 +02:00