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cpu/gd32v: add periph_adc support
This commit is contained in:
Gunar Schorcht
parent
12a05b8fa2
commit
f7949e42fd
@ -1,5 +1,6 @@
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/*
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* Copyright (C) 2020 Koen Zandberg <koen@bergzand.net>
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* 2023 Gunar Schorcht <gunar@schorcht.net>
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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@ -14,6 +15,7 @@
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* @brief CPU specific definitions for internal peripheral handling
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*
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* @author Koen Zandberg <koen@bergzand.net>
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* @author Gunar Schorcht <gunar@schorcht.net>
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*/
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#ifndef PERIPH_CPU_H
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@ -166,6 +168,35 @@ typedef enum {
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GPIO_AF_OUT_OD = 0xf, /**< alternate function output - open-drain */
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} gpio_af_t;
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/**
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* @brief Configure the alternate function for the given pin
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*
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* @param[in] pin pin to configure
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* @param[in] af alternate function to use
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*/
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void gpio_init_af(gpio_t pin, gpio_af_t af);
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/**
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* @brief Configure the given pin to be used as ADC input
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*
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* @param[in] pin pin to configure
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*/
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void gpio_init_analog(gpio_t pin);
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/**
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* @brief Available number of ADC devices
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*/
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#define ADC_DEVS (2U)
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/**
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* @brief ADC channel configuration data
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*/
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typedef struct {
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gpio_t pin; /**< pin connected to the channel */
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uint8_t dev; /**< ADCx - 1 device used for the channel */
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uint8_t chan; /**< CPU ADC channel connected to the pin */
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} adc_conf_t;
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/**
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* @brief GD32V timers have 4 capture-compare channels
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*/
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4
cpu/gd32v/include/vendor/gd32vf103_periph.h
vendored
4
cpu/gd32v/include/vendor/gd32vf103_periph.h
vendored
@ -11529,8 +11529,8 @@ typedef struct { /*!< (@ 0x40002C00) WWDGT Struct
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* @{
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*/
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//#define ADC0_BASE 0x40012400UL
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//#define ADC1_BASE 0x40012800UL
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#define ADC0_BASE 0x40012400UL
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#define ADC1_BASE 0x40012800UL
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//#define AFIO_BASE 0x40010000UL
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//#define BKP_BASE 0x40006C00UL
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//#define CAN0_BASE 0x40006400UL
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212
cpu/gd32v/periph/adc.c
Normal file
212
cpu/gd32v/periph/adc.c
Normal file
@ -0,0 +1,212 @@
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/*
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* Copyright (C) 2016 Engineering-Spirit
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* 2023 Gunar Schorcht
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*
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* This file is subject to the terms and conditions of the GNU Lesser General
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* Public License v2.1. See the file LICENSE in the top level directory for more
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* details.
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*/
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/**
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* @ingroup cpu_gd32v
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* @ingroup drivers_periph_adc
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* @{
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*
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* @file
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* @brief Low-level ADC driver implementation
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author Nick van IJzendoorn <nijzendoorn@engineering-spirit.nl>
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* @author Gunar Schorcht <gunar@schorcht.net>
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*
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* @}
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*/
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#include "cpu.h"
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#include "macros/units.h"
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#include "mutex.h"
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#include "periph/adc.h"
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#include "periph_conf.h"
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/**
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* @brief Maximum allowed ADC clock speed
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*/
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#define MAX_ADC_SPEED MHZ(14)
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/**
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* @brief Allocate locks for all three available ADC devices
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*/
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static mutex_t locks[] = {
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#if ADC_DEVS > 1
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MUTEX_INIT,
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#endif
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MUTEX_INIT
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};
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static inline ADC0_Type *dev(adc_t line)
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{
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switch (adc_config[line].dev) {
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case 0:
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return (ADC0_Type *)ADC0_BASE;
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#if ADC_DEVS > 1
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case 1:
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return (ADC0_Type *)ADC1_BASE;
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#endif
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default:
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assert(0);
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return NULL;
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}
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}
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static inline void prep(adc_t line, adc_res_t res)
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{
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mutex_lock(&locks[adc_config[line].dev]);
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periph_clk_en(APB2, (RCU_APB2EN_ADC0EN_Msk << adc_config[line].dev));
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/* enable the ADC module */
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dev(line)->CTL1 |= ADC0_CTL1_ADCON_Msk;
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/* configure the resolution */
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dev(line)->OVSAMPCTL &= ~ADC0_OVSAMPCTL_DRES_Msk;
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switch (res) {
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case ADC_RES_12BIT:
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dev(line)->OVSAMPCTL |= 0 << ADC0_OVSAMPCTL_DRES_Pos;
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break;
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case ADC_RES_10BIT:
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dev(line)->OVSAMPCTL |= 1 << ADC0_OVSAMPCTL_DRES_Pos;
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break;
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case ADC_RES_8BIT:
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dev(line)->OVSAMPCTL |= 2 << ADC0_OVSAMPCTL_DRES_Pos;
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break;
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case ADC_RES_6BIT:
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dev(line)->OVSAMPCTL |= 3 << ADC0_OVSAMPCTL_DRES_Pos;
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break;
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default:
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break;
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}
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/* check if this channel is an internal ADC channel, if so
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* enable the internal temperature and Vref */
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if (adc_config[line].chan == 16 || adc_config[line].chan == 17) {
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dev(line)->CTL1 |= ADC0_CTL1_TSVREN_Msk;
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}
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}
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static inline void done(adc_t line)
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{
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/* disable the internal temperature and Vref */
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dev(line)->CTL1 &= ~ADC0_CTL1_TSVREN_Msk;
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/* disable the ADC module */
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dev(line)->CTL1 &= ~ADC0_CTL1_ADCON_Msk;
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periph_clk_dis(APB2, (RCU_APB2EN_ADC0EN_Msk << adc_config[line].dev));
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mutex_unlock(&locks[adc_config[line].dev]);
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}
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int adc_init(adc_t line)
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{
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uint32_t clk_div = 2;
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/* check if the line is valid */
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if (line >= ADC_NUMOF) {
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return -1;
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}
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/* lock and power-on the device */
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prep(line, ADC_RES_12BIT);
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/* configure the pin */
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if (adc_config[line].pin != GPIO_UNDEF) {
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gpio_init_analog(adc_config[line].pin);
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}
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/* set clock prescaler to get the maximal possible ADC clock value */
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for (clk_div = 2; clk_div < 8; clk_div += 2) {
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if ((CLOCK_CORECLOCK / clk_div) <= MAX_ADC_SPEED) {
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break;
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}
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}
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RCU->CFG0 &= ~(RCU_CFG0_ADCPSC_2_Msk);
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RCU->CFG0 |= ((clk_div / 2) - 1) << RCU_CFG0_ADCPSC_2_Pos;
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/* resets the selected ADC calibration registers */
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dev(line)->CTL1 |= ADC0_CTL1_RSTCLB_Msk;
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/* check the status of RSTCAL bit */
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while (dev(line)->CTL1 & ADC0_CTL1_RSTCLB_Msk) {}
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/* enable the selected ADC calibration process */
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dev(line)->CTL1 |= ADC0_CTL1_CLB_Msk;
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/* wait for the calibration to have finished */
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while (dev(line)->CTL1 & ADC0_CTL1_CLB_Msk) {}
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/* set all channels to maximum (239.5) cycles for best accuracy */
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dev(line)->SAMPT0 |= 0x00ffffff;
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dev(line)->SAMPT1 |= 0x3fffffff;
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/* we want to sample one channel */
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dev(line)->RSQ0 = 1 << ADC0_RSQ0_RL_Pos;
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/* start sampling from software */
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dev(line)->CTL1 |= ADC0_CTL1_ETERC_Msk | ADC0_CTL1_ETSRC_Msk;
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/* check if the internal channels are configured to use ADC0 */
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if (adc_config[line].chan == 16 || adc_config[line].chan == 17) {
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assert (dev(line) == ADC0);
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}
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/* free the device again */
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done(line);
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return 0;
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}
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int32_t adc_sample(adc_t line, adc_res_t res)
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{
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int sample;
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/* check if the linenel is valid */
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if (line >= ADC_NUMOF) {
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return -1;
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}
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/* check valid resolution */
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dev(line)->OVSAMPCTL &= ~ADC0_OVSAMPCTL_DRES_Msk;
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switch (res) {
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case ADC_RES_12BIT:
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case ADC_RES_10BIT:
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case ADC_RES_8BIT:
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case ADC_RES_6BIT:
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break;
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default:
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return -1;
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}
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/* lock and power on the ADC device */
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prep(line, res);
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/* set conversion channel */
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dev(line)->RSQ2 = adc_config[line].chan;
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/* start conversion and wait for results */
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dev(line)->CTL1 |= ADC0_CTL1_SWRCST_Msk;
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while (!(dev(line)->STAT & ADC0_STAT_EOC_Msk)) {}
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/* finally read sample and reset the STRT bit in the status register */
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sample = (int)dev(line)->RDATA;
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/* the sample is 12 bit even if the resolution is less than 12 bit,
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* scale down the 12 bit value to the requested resolution */
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switch (res) {
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case ADC_RES_10BIT:
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sample = sample >> 2;
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break;
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case ADC_RES_8BIT:
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sample = sample >> 4;
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break;
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case ADC_RES_6BIT:
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sample = sample >> 6;
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break;
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default:
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break;
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}
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/* power off and unlock device again */
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done(line);
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return sample;
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}
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