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Commit Graph

23 Commits

Author SHA1 Message Date
lutgaru
30575f9db8 cpu/cc26x0: refactor vendor code to ensure correct build in riot 2020-11-05 23:32:05 -08:00
Jean Pierre Dudey
f443a8bc84 cpu/cc26xx_cc13xx: enable periph clocks on sleep
Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
2020-10-01 18:38:03 -05:00
Jean Pierre Dudey
447cdebd26 cpu/cc26xx_cc13xx: add & link CCFG configuration
> Allows flahsing CCFG configuration using Kconfig,
formely "make menuconfig".
> Supports cc26x0, cc26x2_cc13x2.
> Can be used to enable bootloader backdoor, to use
cc2538-bsl flashing script.
> Not all options are in Kconfig, most important ones,
others can be added in further commits.
> On cc13xx targets the VDDR high option can be enabled
using Kconfig.
> With this, RIOT can flash blank chips and the firmware
will run just fine.

Signed-off-by: Jean Pierre Dudey <me@jeandudey.tech>
2020-09-27 17:58:11 -05:00
Benjamin Valentin
fae0b00918 cpu/cc26x0: set CPU_HAS_BITBAND
> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.

https://www.ti.com/lit/ug/swcu117i/swcu117i.pdf
2020-08-08 12:44:11 +02:00
Jean Pierre Dudey
ffa5005021
cc26xx_cc13xx: add API to manage peripheral clocks
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-03-23 09:33:53 -05:00
Jean Pierre Dudey
c6e4768997
cc26xx_cc13xx: add PRCM_NONBUF register bank
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-03-23 09:33:23 -05:00
Jean Pierre Dudey
f1af3ae043
cc26x0: add AON_RTC definitions
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
2020-03-16 19:36:54 -05:00
Anton Gerasimov
6790e9e6ca cpu/cc26xx_cc13xx: Fix codespell issues
Signed-off-by: Anton Gerasimov <tossel@gmail.com>
2019-10-29 21:27:00 +01:00
Anton Gerasimov
f6a3f14d22 cpu/cc26x0: Factor out code common for cc26xx/cc13xx family
Signed-off-by: Anton Gerasimov <tossel@gmail.com>
2019-10-29 21:27:00 +01:00
Ben Postman
9a000cf4e6 cpu/cc26x0: Implement uart_mode()
This change required correcting the values for  LCRH_PEN and LRCH_EPS
values defined in cc26x0_uart.h, as they  were incorrect according to
19.8.1.7 of the TI CC26x0 reference manual.

on-behalf-of: @sparkmeter <ben.postman@sparkmeter.io>
2019-06-06 08:46:33 -04:00
MrKevinWeiss
4c9890b269 cpu/cc26x0/i2c: Rework and add error handling
This commit cleans up magic number and defines bitfields.
Adds error codes for ADDR/DATA NACK and ARBLOSS
Adds error handling, it corrects when an error occurs
Protects from flags that could lockup the bus
2019-04-08 11:32:12 +02:00
07eb8554f8 cpu: cc26x0: add periph/i2c implementation 2019-04-08 08:52:43 +02:00
7b6d8d65ff cpu/cc26x0: add missing PERIPH_BASE define 2019-04-08 08:52:43 +02:00
938677cc83 cpu*: fix doxygen grouping 2018-06-11 19:12:02 +02:00
smlng
fd89c3cd9c cpu, cc26x0: fix pm, don't go into cortexm_sleep(0) 2017-10-20 10:51:33 +02:00
smlng
09bc23b41f docu: enhance timer config docu for cc26x0 2017-08-21 10:44:14 +02:00
smlng
91412453ae cpu, cc26x0: fixing low-level timer
- complete rework of periph/timer.c
    - based on TI CC2538 periph/timer.c
2017-07-21 22:20:54 +02:00
0fcc7d3834 cleanup: apply headerguard script output 2017-05-24 17:54:02 +02:00
Joakim Nohlgård
6cda6a6560 periph/cpuid: Unify implementations to a common driver for several platforms 2017-04-05 09:03:49 +02:00
Oleg Hahm
7ee7801c10 *: remove trailing underscores from header guards 2017-01-19 18:30:53 +01:00
Ian Martin
49ae438dd5 doc: eliminate clutter in adc and gpio periph docs 2016-06-29 15:08:32 -04:00
Florent-Valéry
15066e0418 cpu/cc26x0: cpu_clock_init() implementation 2016-04-18 19:00:49 +02:00
Leon M. George
475fb6f84d cpu: add CC26x0-family 2016-04-18 19:00:49 +02:00