openocd configuration file for `stm32f7` relies on probing to find out
FLASH_ADDR. On nucleo-f767zi board probing (`flash probe 0`) fails when
`srst` is asserted, but `srst` needs to be asserted to be able to flash
the `BOARD` when sleeping or after a hardfault.
To circumvent this in boards/common/stm32/dist/stm32f7.cfg we define a new
flash bank with the appropriate fash start address and specify that this is
the flash bank to be used as default configuration instead of the
default by setting FLASH_BANK=4
Added file with clock settings for STM32-F7 CPUs with a core clock of 216MHz,
an external high speed clock of 8 MHz and external low speed clock (32.768kHz)
enabled.
A common configuration file is introduced for stm32f4 with core clock
at 168MHz with HSE at 8MHz, 2 configuration files are introduced to²:
distinguish between clock configuration with and without LSE.
This commit add the connect_assert_srst which requires the SRST to be asserted before trying to connect.
Certain firmwares will cause it to get to a state where flashing fails and the reset button must be pushed at the correct time to recover.
