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https://github.com/RIOT-OS/RIOT.git
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boards/stm32: use shared 180MHz clock config
This commit is contained in:
Hauke Petersen
parent
3182ad21e6
commit
cc90edc373
@ -2,6 +2,9 @@
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USEMODULE += boards_common_nucleo
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INCLUDES += -I$(RIOTBOARD)/common/nucleo/include
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# we use shared STM32 configuration snippets
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INCLUDES += -I$(RIOTBOARD)/common/stm32/include
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# configure the serial terminal
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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72
boards/common/stm32/include/f4/cfg_clock_180_8_1.h
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72
boards/common/stm32/include/f4/cfg_clock_180_8_1.h
Normal file
@ -0,0 +1,72 @@
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/*
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* Copyright (C) 2018 Freie Universität Berlin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_common_stm32
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* @{
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*
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* @file
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* @brief Configure STM32F4 clock to 180MHz using PLL
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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*/
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#ifndef F4_CFG_CLOCK_180_8_1_H
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#define F4_CFG_CLOCK_180_8_1_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 180MHz */
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#define CLOCK_CORECLOCK (180000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (180)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (0)
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/* PLL SAI configuration */
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#define CLOCK_ENABLE_PLL_SAI (1)
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#define CLOCK_PLL_SAI_M (4)
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#define CLOCK_PLL_SAI_N (192)
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#define CLOCK_PLL_SAI_P (8)
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#define CLOCK_PLL_SAI_Q (0)
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/* Use alternative source for 48MHz clock */
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#define CLOCK_USE_ALT_48MHZ (1)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* F4_CFG_CLOCK_180_8_1_H */
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/** @} */
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@ -22,52 +22,13 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f4/cfg_clock_180_8_1.h"
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#include "cfg_spi_divtable.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 180MHz */
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#define CLOCK_CORECLOCK (180000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (180)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (0)
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/* PLL SAI configuration */
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#define CLOCK_ENABLE_PLL_SAI (1)
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#define CLOCK_PLL_SAI_M (4)
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#define CLOCK_PLL_SAI_N (192)
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#define CLOCK_PLL_SAI_P (8)
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#define CLOCK_PLL_SAI_Q (0)
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/* Use alternative source for 48MHz clock */
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#define CLOCK_USE_ALT_48MHZ (1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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@ -216,23 +177,6 @@ static const qdec_conf_t qdec_config[] = {
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 90000000Hz */
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7, /* -> 351562Hz */
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7, /* -> 351562Hz */
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6, /* -> 703125Hz */
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3, /* -> 5625000Hz */
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2 /* -> 11250000Hz */
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},
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{ /* for APB2 @ 180000000Hz */
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7, /* -> 703125Hz */
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7, /* -> 703125Hz */
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7, /* -> 703125Hz */
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4, /* -> 5625000Hz */
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3 /* -> 11250000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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@ -22,52 +22,13 @@
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#include "f4/cfg_clock_180_8_1.h"
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#include "cfg_spi_divtable.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 180MHz */
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#define CLOCK_CORECLOCK (180000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (1)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
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#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
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#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
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/* Main PLL factors */
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#define CLOCK_PLL_M (4)
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#define CLOCK_PLL_N (180)
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#define CLOCK_PLL_P (2)
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#define CLOCK_PLL_Q (0)
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/* PLL SAI configuration */
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#define CLOCK_ENABLE_PLL_SAI (1)
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#define CLOCK_PLL_SAI_M (4)
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#define CLOCK_PLL_SAI_N (192)
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#define CLOCK_PLL_SAI_P (8)
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#define CLOCK_PLL_SAI_Q (0)
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/* Use alternative source for 48MHz clock */
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#define CLOCK_USE_ALT_48MHZ (1)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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@ -178,28 +139,8 @@ static const pwm_conf_t pwm_config[] = {
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 90000000Hz */
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7, /* -> 351562Hz */
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7, /* -> 351562Hz */
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6, /* -> 703125Hz */
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3, /* -> 5625000Hz */
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2 /* -> 11250000Hz */
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},
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{ /* for APB2 @ 180000000Hz */
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7, /* -> 703125Hz */
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7, /* -> 703125Hz */
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7, /* -> 703125Hz */
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4, /* -> 5625000Hz */
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3 /* -> 11250000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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