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boards/stm32f4-based: use shared 168MHz clock conf

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This commit is contained in:
Hauke Petersen 2018-02-13 11:25:32 +01:00
parent cc90edc373
commit 079f3c08d4
9 changed files with 141 additions and 185 deletions
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62
boards/common/stm32/include/f4/cfg_clock_168_16_0.h Normal file
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@ -0,0 +1,62 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 168MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef F4_CFG_CLOCK_168_16_0_H
#define F4_CFG_CLOCK_168_16_0_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (8)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_168_16_0_H */
/** @} */

62
boards/common/stm32/include/f4/cfg_clock_168_8_1.h Normal file
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@ -0,0 +1,62 @@
/*
* Copyright (C) 2018 Freie Universität Berlin
*
* This file is subject to the terms and conditions of the GNU Lesser
* General Public License v2.1. See the file LICENSE in the top level
* directory for more details.
*/
/**
* @ingroup boards_common_stm32
* @{
*
* @file
* @brief Configure STM32F4 clock to 168MHz using PLL
*
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
*/
#ifndef F4_CFG_CLOCK_168_8_1_H
#define F4_CFG_CLOCK_168_8_1_H
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* F4_CFG_CLOCK_168_8_1_H */
/** @} */

3
boards/f4vi1/Makefile.include
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@ -2,6 +2,9 @@
export CPU = stm32f4
export CPU_MODEL = stm32f415rg
# we use shared STM32 configuration snippets
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

34
boards/f4vi1/include/periph_conf.h
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@ -11,7 +11,7 @@
* @{
*
* @file
* @name Peripheral MCU configuration for the F4VI1 board
* @name Peripheral MCU configuration for the F4VI1 board
*
* @author Stefan Pfeiffer <pfeiffer@inf.fu-berlin.de>
* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
@ -22,42 +22,12 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f4/cfg_clock_168_16_0.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (8)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name Timer configuration
* @{

3
boards/msbiot/Makefile.include
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@ -2,6 +2,9 @@
export CPU = stm32f4
export CPU_MODEL = stm32f415rg
# we use shared STM32 configuration snippets
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
#define the default port depending on the host OS
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

53
boards/msbiot/include/periph_conf.h
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@ -20,42 +20,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f4/cfg_clock_168_16_0.h"
#include "cfg_spi_divtable.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (16000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (0)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (8)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name Timer configuration
* @{
@ -193,28 +164,8 @@ static const uart_conf_t uart_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

53
boards/nucleo-f429zi/include/periph_conf.h
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@ -22,42 +22,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
#include "cfg_spi_divtable.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 180MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 45MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 90MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name Timer configuration
* @{
@ -168,28 +139,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,

3
boards/stm32f4discovery/Makefile.include
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@ -2,6 +2,9 @@
export CPU = stm32f4
export CPU_MODEL = stm32f407vg
# we use shared STM32 configuration snippets
INCLUDES += -I$(RIOTBOARD)/common/stm32/include
# set default port depending on operating system
PORT_LINUX ?= /dev/ttyUSB0
PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.SLAB_USBtoUART*)))

53
boards/stm32f4discovery/include/periph_conf.h
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@ -21,42 +21,13 @@
#define PERIPH_CONF_H
#include "periph_cpu.h"
#include "f4/cfg_clock_168_8_1.h"
#include "cfg_spi_divtable.h"
#ifdef __cplusplus
extern "C" {
#endif
/**
* @name Clock settings
*
* @note This is auto-generated from
* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
* @{
*/
/* give the target core clock (HCLK) frequency [in Hz],
* maximum: 168MHz */
#define CLOCK_CORECLOCK (168000000U)
/* 0: no external high speed crystal available
* else: actual crystal frequency [in Hz] */
#define CLOCK_HSE (8000000U)
/* 0: no external low speed crystal available,
* 1: external crystal available (always 32.768kHz) */
#define CLOCK_LSE (1)
/* peripheral clock setup */
#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
#define CLOCK_APB1_DIV RCC_CFGR_PPRE1_DIV4 /* max 42MHz */
#define CLOCK_APB1 (CLOCK_CORECLOCK / 4)
#define CLOCK_APB2_DIV RCC_CFGR_PPRE2_DIV2 /* max 84MHz */
#define CLOCK_APB2 (CLOCK_CORECLOCK / 2)
/* Main PLL factors */
#define CLOCK_PLL_M (4)
#define CLOCK_PLL_N (168)
#define CLOCK_PLL_P (2)
#define CLOCK_PLL_Q (7)
/** @} */
/**
* @name Timer configuration
* @{
@ -188,28 +159,8 @@ static const pwm_conf_t pwm_config[] = {
/**
* @name SPI configuration
*
* @note The spi_divtable is auto-generated from
* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
* @{
*/
static const uint8_t spi_divtable[2][5] = {
{ /* for APB1 @ 42000000Hz */
7, /* -> 164062Hz */
6, /* -> 328125Hz */
4, /* -> 1312500Hz */
2, /* -> 5250000Hz */
1 /* -> 10500000Hz */
},
{ /* for APB2 @ 84000000Hz */
7, /* -> 328125Hz */
7, /* -> 328125Hz */
5, /* -> 1312500Hz */
3, /* -> 5250000Hz */
2 /* -> 10500000Hz */
}
};
static const spi_conf_t spi_config[] = {
{
.dev = SPI1,