The interval load value was only set to 0xffff regardless of the counter
mode used which mad the 32bit timer apparently stop after 0xffff (it
would never reach values >0xffff).
When a GPTM is configured to one of the 32-bit modes, TAILR appears as a
32-bit register (the upper 16-bits correspond to the contents of the
GPTM Timer B Interval Load (TBILR) register). In a 16-bit mode, the
upper 16 bits of this register read as 0s and have no effect on the
state of TBILR.
Thsi commit set the correct value for TAILR depending on the configured
timer mode.
Seems like the Interrupt flag for a Capture/Compare channel gets set when
- the CC-value is reached
- the timer resets before the CC value is reached.
We only want the first event and ignore the second one. Unfortunately I did
not find a way to disable the second event type, so it is filtered in software.
That is we need to
- ignore the CC-interrupts when the COUNT register register is reset
- ignore the CC-interrupts > TOP value/ARR (auto-reload register)
> A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region.
> The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. A
https://www.mouser.com/datasheet/2/405/lm4f120h5qr-124014.pdf
> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.
https://www.ti.com/lit/ug/swcu117i/swcu117i.pdf
> Bit-banding is supported in order to reduce the execution time for
> read-modify-write (RMW) operations to memory.
> With bit-banding, certain regions in the memory map
> (SRAM and peripheral space) can use address aliases to access
> individual bits in one atomic operation.
https://www.ti.com/lit/ug/swcu185d/swcu185d.pdf
If we disable an external interrupt, GPIO events that would generate an interrupt will still set the interrupt flag.
That means once we enable the interrupt again, a stale interrupt will be triggered.
This is surprising and probably not what the user wants, unfortunately the API documentation is not very clear about what to expect.
There is however no way to drop those intermediate interrupts with the current API.
Ignoring the events that occurred while the GPIO interrupt were disabled is probably the right (and expected) thing to.
Both tests/pthread_tls and tests/prng_sha256prng fail without this, but
other platforms run fine with their defaults. Lets consider the higher
value a better default.
Previously the setting the alarm would overwrite the overflow callback
and vice versa.
Since we can only set one alarm in hardware, always set the alarm to the
closest event of the two.
Move common code into helper functions and extract the commands
that differ between normal and RWWEE page reading / writing.
This cuts down on `#ifdef` use.
The RTC and RTT share the same peripheral, so they can also
share the same code.
This is needed to integrate the Tamper Detection into common
RTC/RTT code.
Since former ESP32 toolchain versions used POSIX threads, module `pthread` was required. The built-in `cxa_ctor_guards` had to be replaced since they used the `pthread_once` function for singleton objects initialization where the parameter `once` was of incompatible type with that provided by RIOT's `pthread` module. The current ESP32 toolchain version no longer uses POSIX threads. The dependency on module `pthread` as well as according C++ hacks can be removed.
We don't need to read-modify-write the CTRLA register to disable
the UART.
The entire CTRLA register is re-written just a few lines below, so
we can just set it to 0 to disable the UART.
There is also no need to reset the UART since we re-write all config
registers in init.
If a timer triggers while the idle thread is running, previously a stack
overflow was triggered. This commit increases the idle threads stack size if
xtimer is used.
- Added missing wait for TX flush
- Grouped access to the same registers of the Ethernet PHY to reduce accesses.
(The compiler won't optimize accesses to `volatile`, as defined in the C
standard.)
- Add missing `volatile` to DMA descriptor, as memory is also accessed by the
DMA without knowledge of the compiler
- Dropped `__attribute__((packed))` from DMA descriptor
- The DMA descriptor fields need to be aligned on word boundries to
properly function
- The compiler can now more efficiently access the fields (safes ~300 B ROM)
- Moved the DMA descriptor struct and the flags to `periph_cpu.h`
- This allows Doxygen documentation being build for it
- Those types and fields are needed for a future PTP implementation
- Renamed DMA descriptor flags
- They now reflect to which field in the DMA descriptor they refer to, so
that confusion is avoided
- Added documentation to the DMA descriptor and the corresponding flags
The Atmel I2C peripheral supports arbitrary I2C frequencies.
Since the `i2c_speed_t` enum just encodes the raw frequency values,
we can just use them in the peripheral definition.
We just have to remove the switch-case block that will generate an error
for values outside of `i2c_speed_t`.
The available GPIO ports may also differ within a family. Therefore, the vendor definitions GPIO* are used instad of CPU_FAM_STM definitions to determine which ports are available for a certain MCU.
fcntl(fd, F_SETOWN, getpid()); doesn't seem to work on Linux
to get generate a signal when an event on the GPIO fd occurs.
So fall back to the same method as on OS X and call poll() in
a child process.
select() can not listen to POLLPRI events which are used by the
Kernel's GPIO API.
In preparation for that, rewrite async_read() to use poll() instead
of select().
The PendSV interrupt is used to request a scheduling operation. An
interrupt during the idle sleep can re-request the PendSV interrupt,
while the PendSV is still busy scheduling the next thread. This clears
the request after sleep to prevent triggering an extra PendSV interrupt
after the current PendSV handler finished.
Not all MCUs ≥ Cortex-M3 provide the Bit-Banding feature.
It is up to the manufacturer to implement it.
Instead, rely on the CPU_HAS_BITBAND being set in `periph_cpu.h`.
A race condition is present where an IRQ is serviced between the
priority increase of the PENDSV and the sleep. When the IRQ
is serviced before the WFI sleep, the core will sleep until the next
IRQ and the thread activated by the IRQ will not be scheduled until
a new IRQ triggers.
This commit wraps an IRQ disable and restore around the priority
modification and sleep to prevent interrupts from being serviced until
the WFI call returns.
- Make use of the fact that gpio_init_af() does not need prior call to
gpio_init() for all STM32 families anymore and drop call to gpio_init()
- Initialize the UART periph first, before initializing the pins
- While uninitialized, the UART periph will send signal LOW to TXD. This
results in a start bit being picked up by the other side.
- Instead, we do not connect the UART periph to the pins until it is
initialized, so that the TXD level will already be HIGH when the pins
are attached.
- This results in no more garbage being send during initialization
- Do not set an intermediate mode, prepare correct mode settings in a temporary
variable
- Consistently enabled the GPIO periph in gpio_init_af()
- Previously, STM32 F1 did not require a separate call to gpio_init() prior
to a call of gpio_init_af(), but other STM32 families did
- Now, gpio_init_af() can be used without gpio_init() consistently
- STM32 F1: Do not touch ODR for non input pins
- For input pins, this enables / disabled pull up resistors. For outputs,
this register should remain untouched (according to API doc)
- Add libstdcpp feature to indicate a platform is providing a libstdc++
implementation ready for use
- The existing cpp feature now only indicates a working C++ toolchain without
libstdc++. (E.g. still useful for the Arduino compatibility layer.)
- Added libstdcpp as required feature were needed
- Added some documentation on C++ on RIOT
The `ldr r1, =sched_active_thread` instruction couldn't be assembled with
LTO, as the no immediate offset could be found to construct the address of
`sched_active_thread`. This commit instructs the assembler to generate a
literate pool which can be used to construct the address. While this issue
was only triggered during LTO, it theoretically could also pop up without LTO
due to unrelated changes. Thus, it is a good idea to create the literate pool
even without LTO enabled.
cpu/stm32/qdec: test if callback pointer is set
Callback pointer is not tested and could result in a hard fault
if the pointer is NULL.
Thus only activate interrupt if a callback provided.
Signed-off-by: Gilles DOFFE <g.doffe@gmail.com>
The EFM32 uses the provided _SILICON_LABS_32B_SERIES_0 and
_SILICON_LABS_32B_SERIES_1 definitions to enable or disable certain
code. With the introduction of new MCUs, there is also the
_SILICON_LABS_32B_SERIES_2 definition.
This PR ensures that the defines are explicit, and that #else
statements don't target the wrong series.
