- Make use of the fact that gpio_init_af() does not need prior call to
gpio_init() for all STM32 families anymore and drop call to gpio_init()
- Initialize the UART periph first, before initializing the pins
- While uninitialized, the UART periph will send signal LOW to TXD. This
results in a start bit being picked up by the other side.
- Instead, we do not connect the UART periph to the pins until it is
initialized, so that the TXD level will already be HIGH when the pins
are attached.
- This results in no more garbage being send during initialization
- Do not set an intermediate mode, prepare correct mode settings in a temporary
variable
- Consistently enabled the GPIO periph in gpio_init_af()
- Previously, STM32 F1 did not require a separate call to gpio_init() prior
to a call of gpio_init_af(), but other STM32 families did
- Now, gpio_init_af() can be used without gpio_init() consistently
- STM32 F1: Do not touch ODR for non input pins
- For input pins, this enables / disabled pull up resistors. For outputs,
this register should remain untouched (according to API doc)
The `ldr r1, =sched_active_thread` instruction couldn't be assembled with
LTO, as the no immediate offset could be found to construct the address of
`sched_active_thread`. This commit instructs the assembler to generate a
literate pool which can be used to construct the address. While this issue
was only triggered during LTO, it theoretically could also pop up without LTO
due to unrelated changes. Thus, it is a good idea to create the literate pool
even without LTO enabled.
cpu/stm32/qdec: test if callback pointer is set
Callback pointer is not tested and could result in a hard fault
if the pointer is NULL.
Thus only activate interrupt if a callback provided.
Signed-off-by: Gilles DOFFE <g.doffe@gmail.com>
The EFM32 uses the provided _SILICON_LABS_32B_SERIES_0 and
_SILICON_LABS_32B_SERIES_1 definitions to enable or disable certain
code. With the introduction of new MCUs, there is also the
_SILICON_LABS_32B_SERIES_2 definition.
This PR ensures that the defines are explicit, and that #else
statements don't target the wrong series.
Other archs use `_sheap` and `_eheap` to mark the start and end of
the heap.
fe310 uses `_heap_start` and `_heap_end`, so platform independent
code that wants to make use of this will needlessly fail.
For compatibility with common code, name them the same on fe310.
>All of them are features of each ESP SoC and have not to be configured by the
board definition.
Signed-off-by: Jean Pierre Dudey <jeandudey@hotmail.com>
Co-authored-by: Gunar Schorcht <gunar@schorcht.net>
- Use `irq_enable()` over `bl irq_enable`, as `irq_enable()` is an inline
function and not a C function any more
- Drop `__attribute__((naked))` qualifier
- It must be used with the declaration of the function, but there it is
missing. (And it cannot be added there, as this function would need to
be implemented as "naked" by every platform; which is impossible for
platforms not supporting `__attribute__((naked))`.)
- Only functions consisting completely of basic asm may be marked as naked.
But both the assembly used to trigger the SVC interrupt as well as the
assembly used in `irq_enable()` are extended asm, not basic asm
- Use ` UNREACHABLE();` over a custom asm construct
There are common features that can be used by ESP32 as well as ESP8266, for example the `esp_wifi` module. To be able to test for any ESP SoC, feature `arch_esp` is introduced.
- Updated to inline-able IRQ API
- Improved robustness of functions
- Added memory barrier to prevent the compiler from moving code outside of
a critical section guarded by irq_disable() ... irq_restore()
- Reduced overhead of `irq_disable()`
- After clearing the global interrupt enable (GIE) bit, IRQs remain enabled
for up to one CPU cycle
- The previous implementation just added a nop to fill that cycle
- This implementation uses the cycle for masking the return value
- Reduced overhead of `irq_restore()`
- Now only one CPU cycle is needed
- `irq_disable()`, `irq_restore()`, and `irq_enable()` work now in constant time
All bits in the ICSR register in the cortexm system control block are
either read-only or don't have an effect when writing a zero. A
read-modify-write cycle is thus not required when writing bit flags in
the register. This commit removes the reads in the read-modify-store
patterns for this register.
The spi scalar calculation tool for the kinetis family is stand-alone
and doesn't use the RIOT headers. It doesn't include the ARRAY_SIZE
macro from the RIOT headers. This commit adds a local definition of the
ARRAY_SIZE macro
Currently only samd21 used the 32 kHz clock for EXTI which makes it miss fast events.
All newer members of the family use the MAIN clock.
While touching this, also make the clock source configurable to this can be overwritten,
e.g. in the board config if desired.
