The internal DC/DC converter is more efficient compared to the LDO
regulator. The downside of the DC/DC converter is that it requires an
external inductor to be present on the board. Enabling the DC/DC
converter is guarded with NRF5X_ENABLE_DCDC, this macro must be defined
if the DC/DC converter is to be enabled.
This implements a basic Real Time Clock based on TIM2.
As the timer is too fast and wraps around after just 8 bits, it is
not used directly. Instead TIM2 is responsible for providing a 1 Hz
tick by generating an alarm every second.
The current time data is kept in the `.noinit` section, so it will survive
a reboot, but the clock will not be updated while the bootloader runs, so
expect inaccuracies.
By using a custom EPOCH for the RTC implementation, we can extend the
range of the 32 bit counter based RTC by 118 years.
It also reduces the code size compared to the stdlib based POSIX functions.
To be able to define common configurations for all ESP CPUs, the CPU specific configuration cpu_conf.h has to include a common configuration. For that purpose cpu_conf.h in cpu/esp_common is renamed to cpu_conf_common.h and included in CPU specific configurations.
The split between GEN2_ULP32K and GEN3_ULP32K was introduced to fix
a failure in tests/periph_wdt when the external oscillator was used.
By not running the external oscillator on demand, the failure can no
longer be observed, so default GEN3_ULP32K to GEN2_ULP32K.
The lpc23xx MCU has up to three I2C interfaces.
This adds a driver for it.
The peripheral works in interrupt mode, each change of the state machine
will generate an interrupt.
The response to the states are laid out in the data sheet.
This replaces the old driver that was removed in c560e28eb6
All the more recent vendor files have them, so include them for samr30 too.
It is expected for this to become obsolete with the next vendor file update.
During the write access to the SPI flash, the IROM cache is not available and only code from the IRAM can be executed. Therefore, the code of file system implementations which access the SPI flash must reside in IRAM.
For consistency, use named GCLKs.
- `SAM0_GCLK_32KHZ` will always be 2 for samd21
- `SAM0_GCLK_MAIN` will always be 0
So no change in functionality, just makes the code easier to understand.
