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boards: add stm32f030f4-demo
The board is a very cheap (< 1€) breakout board for the stm32f030f4 MCU.
This commit is contained in:
Benjamin Valentin
Benjamin Valentin
parent
6db9421057
commit
a97e0543cb
3
boards/stm32f030f4-demo/Makefile
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3
boards/stm32f030f4-demo/Makefile
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MODULE = board
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include $(RIOTBASE)/Makefile.base
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10
boards/stm32f030f4-demo/Makefile.features
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10
boards/stm32f030f4-demo/Makefile.features
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CPU = stm32f0
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CPU_MODEL = stm32f030f4
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# Put defined MCU peripherals here (in alphabetical order)
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FEATURES_PROVIDED += periph_adc
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FEATURES_PROVIDED += periph_pwm
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FEATURES_PROVIDED += periph_timer
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FEATURES_PROVIDED += periph_uart
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FEATURES_PROVIDED += periph_spi
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FEATURES_PROVIDED += periph_rtc
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18
boards/stm32f030f4-demo/Makefile.include
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boards/stm32f030f4-demo/Makefile.include
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INCLUDES += -I$(RIOTBOARD)/common/stm32/include
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# configure the serial terminal
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PORT_LINUX ?= /dev/ttyACM0
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PORT_DARWIN ?= $(firstword $(sort $(wildcard /dev/tty.usbmodem*)))
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# setup serial terminal
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include $(RIOTMAKE)/tools/serial.inc.mk
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# stm32 boards can become un-flashable after a hardfault,
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# use connect_assert_srst to always be able to flash or reset the boards.
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export OPENOCD_RESET_USE_CONNECT_ASSERT_SRST ?= 1
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# all Nucleo boards have an on-board ST-link adapter
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DEBUG_ADAPTER ?= stlink
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# stlink use openocd
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include $(RIOTMAKE)/tools/openocd.inc.mk
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30
boards/stm32f030f4-demo/board.c
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30
boards/stm32f030f4-demo/board.c
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_stm32f030f4-demo
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* @{
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*
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* @file
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* @brief Board initialization code for the stm32f030f4-demo board.
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*
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* @}
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*/
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#include "board.h"
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#include "cpu.h"
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#include "periph/gpio.h"
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void board_init(void)
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{
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cpu_init();
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gpio_init(LED0_PIN, GPIO_OUT);
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LED0_OFF;
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}
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54
boards/stm32f030f4-demo/doc.txt
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54
boards/stm32f030f4-demo/doc.txt
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/**
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@defgroup boards_stm32f030f4-demo STM32F030F4 Demo Board
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@ingroup boards
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@brief Support for the STM32F030F4 Demo Board
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## Overview
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The STM32F030F4 Demo Board is a very cheap breakout board for the STM32F030F4 MCU.
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## Hardware
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### MCU
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| MCU | STM32F030R4 |
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|:---------- |:--------------------- |
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| Family | ARM Cortex-M0 |
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| Vendor | ST Microelectronics |
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| RAM | 4Kb |
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| Flash | 16Kb |
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| Frequency | up to 48MHz |
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| FPU | no |
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| Timers | 8 (2x watchdog, 1 SysTick, 5x 16-bit) |
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| ADCs | 1x 12-bit |
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| UARTs | 6 |
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| SPIs | 1 |
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| I2Cs | 1 |
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| RTC | 1 |
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| Vcc | 2.0V - 3.6V |
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| Datasheet | [Datasheet](https://www.st.com/en/microcontrollers-microprocessors/stm32f030f4.html) |
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| Reference Manual | [Reference Manual](https://www.st.com/resource/en/datasheet/stm32f030f4.pdf) |
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| Programming Manual | [Programming Manual](http://www.st.com/resource/en/programming_manual/dm00051352.pdf) |
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## Flashing the device
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The STM32F030F4 Demo Board board does not include a programmer.
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You have to connect a separate ST-Link programmer to the (SW)DIO, (SW)CLK, GND and
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NRST pins on the board.
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If you want a serial terminal, you have to connect a separate USB-Serial adapter to
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the RX and TX pins on the board.
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The easiest way to program the board is to use OpenOCD. Once you have installed
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OpenOCD (look [here](https://github.com/RIOT-OS/RIOT/wiki/OpenOCD) for
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installation instructions), you can flash the board simply by typing
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```
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make BOARD=stm32f030f4-demo flash
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```
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and debug via GDB by simply typing
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```
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make BOARD=stm32f030f4-demo debug
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```
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*/
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61
boards/stm32f030f4-demo/include/board.h
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61
boards/stm32f030f4-demo/include/board.h
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/*
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* Copyright (C) 2019 Benjamin Valentin
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_stm32f030f4-demo
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*
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* This board can be bought very cheaply (< 1€) on sites like eBay or
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* AliExpress.
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*
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* @brief Support for the STM32F030F4 Demo Board
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* @{
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*
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* @file
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* @brief Pin definitions and board configuration options
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*
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef BOARD_H
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#define BOARD_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Xtimer configuration
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* @{
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*/
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#define XTIMER_WIDTH (16)
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/** @} */
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/**
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* @name LED pin definitions and handlers
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* @{
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*/
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#define LED0_PORT GPIOA
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#define LED0_PIN GPIO_PIN(PORT_A, 4)
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#define LED0_MASK (1 << 4)
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#define LED0_ON (LED0_PORT->BSRR = (LED0_MASK << 16))
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#define LED0_OFF (LED0_PORT->BSRR = (LED0_MASK << 0))
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#define LED0_TOGGLE (LED0_PORT->ODR ^= LED0_MASK)
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/** @} */
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/**
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* @brief Initialize board specific hardware, including clock, LEDs and std-IO
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*/
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void board_init(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* BOARD_H */
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/** @} */
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189
boards/stm32f030f4-demo/include/periph_conf.h
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189
boards/stm32f030f4-demo/include/periph_conf.h
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/*
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* Copyright (C) 2016 Inria
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*
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* This file is subject to the terms and conditions of the GNU Lesser
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* General Public License v2.1. See the file LICENSE in the top level
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* directory for more details.
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*/
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/**
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* @ingroup boards_stm32f030f4-demo
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* @{
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*
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* @file
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* @brief Peripheral MCU configuration for the stm32f030f4-demo board
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*
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* @author Hauke Petersen <hauke.petersen@fu-berlin.de>
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* @author José Ignacio Alamos <jialamos@uc.cl>
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* @author Alexandre Abadie <alexandre.abadie@inria.fr>
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* @author Benjamin Valentin <benpicco@googlemail.com>
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*/
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#ifndef PERIPH_CONF_H
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#define PERIPH_CONF_H
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#include "periph_cpu.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @name Clock settings
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*
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* @note This is auto-generated from
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* `cpu/stm32_common/dist/clk_conf/clk_conf.c`
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* @{
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*/
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/* give the target core clock (HCLK) frequency [in Hz],
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* maximum: 48MHz */
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#define CLOCK_CORECLOCK (48000000U)
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/* 0: no external high speed crystal available
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* else: actual crystal frequency [in Hz] */
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#define CLOCK_HSE (8000000U)
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/* 0: no external low speed crystal available,
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* 1: external crystal available (always 32.768kHz) */
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#define CLOCK_LSE (0)
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/* peripheral clock setup */
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#define CLOCK_AHB_DIV RCC_CFGR_HPRE_DIV1
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#define CLOCK_AHB (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB1_DIV RCC_CFGR_PPRE_DIV1 /* max 48MHz */
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#define CLOCK_APB1 (CLOCK_CORECLOCK / 1)
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#define CLOCK_APB2 (CLOCK_APB1)
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/* PLL factors */
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#define CLOCK_PLL_PREDIV (1)
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#define CLOCK_PLL_MUL (6)
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/** @} */
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/**
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* @name Timer configuration
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* @{
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*/
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static const timer_conf_t timer_config[] = {
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{
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.dev = TIM1,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB2ENR_TIM1EN,
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.bus = APB2,
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.irqn = TIM1_CC_IRQn
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},
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{
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.dev = TIM3,
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.max = 0x0000ffff,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.bus = APB1,
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.irqn = TIM3_IRQn
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},
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};
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#define TIMER_0_ISR (isr_tim1_cc)
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#define TIMER_1_ISR (isr_tim3)
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#define TIMER_NUMOF ARRAY_SIZE(timer_config)
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/** @} */
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/**
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* @name UART configuration
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* @{
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*/
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static const uart_conf_t uart_config[] = {
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{
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.dev = USART1,
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.rcc_mask = RCC_APB2ENR_USART1EN,
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.rx_pin = GPIO_PIN(PORT_A, 10),
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.tx_pin = GPIO_PIN(PORT_A, 9),
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.rx_af = GPIO_AF1,
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.tx_af = GPIO_AF1,
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.bus = APB2,
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.irqn = USART1_IRQn
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}
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};
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#define UART_0_ISR (isr_usart1)
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#define UART_NUMOF ARRAY_SIZE(uart_config)
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/** @} */
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/**
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* @name PWM configuration
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* @{
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*/
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static const pwm_conf_t pwm_config[] = {
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{
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.dev = TIM3,
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.rcc_mask = RCC_APB1ENR_TIM3EN,
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.chan = { { .pin = GPIO_PIN(PORT_A, 6), .cc_chan = 0},
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{ .pin = GPIO_PIN(PORT_A, 7), .cc_chan = 1},
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{ .pin = GPIO_UNDEF, .cc_chan = 0},
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{ .pin = GPIO_UNDEF, .cc_chan = 0} },
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.af = GPIO_AF1,
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.bus = APB1
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}
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};
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#define PWM_NUMOF ARRAY_SIZE(pwm_config)
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/** @} */
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/**
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* @name SPI configuration
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*
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* @note The spi_divtable is auto-generated from
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* `cpu/stm32_common/dist/spi_divtable/spi_divtable.c`
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* @{
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*/
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static const uint8_t spi_divtable[2][5] = {
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{ /* for APB1 @ 48000000Hz */
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7, /* -> 187500Hz */
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6, /* -> 375000Hz */
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5, /* -> 750000Hz */
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2, /* -> 6000000Hz */
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1 /* -> 12000000Hz */
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},
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{ /* for APB2 @ 48000000Hz */
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7, /* -> 187500Hz */
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6, /* -> 375000Hz */
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5, /* -> 750000Hz */
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2, /* -> 6000000Hz */
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1 /* -> 12000000Hz */
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}
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};
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static const spi_conf_t spi_config[] = {
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{
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.dev = SPI1,
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.mosi_pin = GPIO_PIN(PORT_A, 7),
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.miso_pin = GPIO_PIN(PORT_A, 6),
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.sclk_pin = GPIO_PIN(PORT_A, 5),
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.cs_pin = GPIO_PIN(PORT_B, 1),
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.af = GPIO_AF0,
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.rccmask = RCC_APB2ENR_SPI1EN,
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.apbbus = APB2
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},
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};
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#define SPI_NUMOF ARRAY_SIZE(spi_config)
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/** @} */
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/**
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* @name ADC configuration
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* @{
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*/
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#define ADC_CONFIG { \
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{ GPIO_PIN(PORT_A, 0), 0 }, \
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{ GPIO_PIN(PORT_A, 1), 1 }, \
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{ GPIO_PIN(PORT_A, 2), 2 }, \
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{ GPIO_PIN(PORT_A, 3), 3 }, \
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{ GPIO_PIN(PORT_A, 4), 4 },\
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{ GPIO_PIN(PORT_A, 5), 5 } \
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}
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#define ADC_NUMOF (6)
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/** @} */
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#ifdef __cplusplus
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}
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#endif
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#endif /* PERIPH_CONF_H */
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/** @} */
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